Patents Assigned to NXP B.V.
  • Patent number: 12212431
    Abstract: The present invention relates to a CAN node being configured to predict, based on the at least one response message and a reference response, a fault of the CAN network and to determine a fault location of the predicted fault of the CAN network. The present disclosure also relates to a CAN system and a method for the CAN node.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: January 28, 2025
    Assignee: NXP B.V.
    Inventors: Clemens Gerhardus Johannes de Haas, Matthias Berthold Muth, Gerald Kwakernaat, Lucas Pieter Lodewijk van Dijk
  • Patent number: 12212074
    Abstract: An integrated circuit comprising a package, phased antenna array and die. The die comprises a plurality of unit cells, wherein each unit cell is divided into quadrants. Each quadrant comprises a receiver terminal located on a first axis, and a transmitter terminal located on a second axis, wherein the first axis is orthogonal to the second axis, and there is mirror symmetry between the nearest neighbour quadrants in the unit cell. The package comprises a plurality of pairs of feed lines, each pair of feed lines comprising a receiver feed line and a transmitter feed line. The receiver feed line is connected to one of the receiver terminals and the transmitter feed line is connected to the transmitter terminal in the same die quadrant. The receiver feed line is orthogonal to the transmitter feed line. Each antenna element is coupled to a respective pair of feed lines.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: January 28, 2025
    Assignee: NXP B.V.
    Inventors: Jan Willem Bergman, Mustafa Acar, Antonius Hendrikus Jozef Kamphuis, Dominicus Martinus WilHelmus Leenaerts, Rajesh Mandamparambil, Paul Mattheijssen
  • Patent number: 12212660
    Abstract: A method is provided for challenge-response authentication between a verifier and a prover. In the method, a challenge is received from the verifier, the challenge for verifying an identity of the prover. The challenge is computed using a first verifier key. The prover computes a response to the challenge using a first prover key. The prover also computes a delay time for delaying transmission of the response to the verifier using a second prover key and a delay computation function. The response is transmitted by the prover to the verifier at the computed delay time. The response is verifiable by the verifier using the first verifier key. An arrival time of the response is verifiable by the verifier using a second verifier key. In another embodiment, a device for providing a delayed response is provided.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: January 28, 2025
    Assignee: NXP B.V.
    Inventors: Nikita Veshchikov, Christian Schwar
  • Patent number: 12212430
    Abstract: The present invention relates to a controller area network, CAN, transceiver comprising a monitoring unit configured to execute either a first process for detecting an error at the CAN signal lines or a different second process for detecting an error at the transceiver or the CAN signal lines depending on a mode of the CAN transceiver detected by the monitoring unit. The present invention also relates to a method for the CAN transceiver.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: January 28, 2025
    Assignee: NXP B.V.
    Inventor: Lucas Pieter Lodewijk van Dijk
  • Patent number: 12211840
    Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: January 28, 2025
    Assignee: NXP B.V.
    Inventors: Jozef Reinerus Maria Bergervoet, Xin Yang, Mark Pieter van der Heijden, Lukas Frederik Tiemeijer, Alessandro Baiano
  • Patent number: 12205942
    Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 21, 2025
    Assignee: NXP B.V.
    Inventors: Guido Wouter Willem Quax, Dongyong Zhu, Feng Cong, Tingting Pan
  • Patent number: 12206521
    Abstract: An apparatus for a CAN transceiver configured to couple to a CAN bus and generate receive-data based on signals therefrom and generate signals on the CAN bus in response to transmit-data received from a CAN controller, wherein the apparatus is configured to: receive the receive-data comprising a plurality of bits; and for each of one or more bits of the receive-data, sample at a respective sample time to determine a respective value of each of the one or more bits; and with an edge detector determine, during a respective edge detector window, the occurrence of an edge in the receive-data and generate metadata indicative thereof, wherein the edge detector window comprises a period of time that includes the sample time; and wherein the apparatus is configured to determine whether transmit-data is compliant with one or more rules based on the respective values and the metadata.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: January 21, 2025
    Assignee: NXP B.V.
    Inventors: Rolf van de Burgt, Bernd Uwe Gerhard Elend, Thierry G. C. Walrant, Dennis aan de Stegge
  • Patent number: 12204011
    Abstract: A method is provided for radar ranging using an IR-UWB radar transceiver. The range is determined by measuring a time required by a transmitted pulse to be reflected by an object and returned to the transceiver. The method includes transmitting a ranging signal having a predetermined sequence of positive and negative pulses using a transmitter of the transceiver. A receiver of the transceiver receives a signal having a reflected portion and a feedthrough portion. In the method, the receiver cancels the feedthrough portion using a delayed pulse polarity signal such that when the delayed pulse polarity signal is multiplied and accumulated with the received signal, the feedthrough portion is canceled, and the reflected portion is amplified. In another embodiment, a transceiver is provided that cancels the feedthrough portion while amplifying the reflected portion. Cancelling the feedthrough portion allows short-range operation by removing a blind range of the transceiver.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: January 21, 2025
    Assignee: NXP B.V.
    Inventors: Abdul Wahid Abdul Kareem, Radha Srinivasan, Brima Babatunde Ibrahim
  • Patent number: 12206237
    Abstract: A semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: January 21, 2025
    Assignee: NXP B.V.
    Inventors: Dolphin Abessolo Bidzo, Shailesh Kulkarni, Juan Felipe Osorio Tamayo
  • Patent number: 12205950
    Abstract: An integrated circuit includes a first semiconductor device with an N type region biased by a first terminal and a second semiconductor device with a second region. An N type guard region is located laterally between the N type region of the first semiconductor device and the second region. A P type region is isolated in the N type guard region and is biased by a second terminal. The N type guard region is either electrically coupled to the second terminal through a resistor circuit or is characterized as floating.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: January 21, 2025
    Assignee: NXP B.V.
    Inventor: Guido Wouter Willem Quax
  • Patent number: 12197558
    Abstract: A method is provided for authenticating an electronic device. The method includes obtaining a message to be sent. A plurality of error locations is determined for errors to be intentionally introduced into the message. The plurality of error locations is communicated to a verifier device. A bit at each of the error locations of the plurality of error locations is inverted in the message in the electronic device to generate a message with intentionally introduced errors. The plurality of error locations is sent to a verifier device. The message with the intentionally introduced errors is transmitted to the verifier device. The verifier device is enabled to use the plurality of error locations to authenticate the electronic device by comparing errors detected in the transmitted message to the plurality of error locations. The method provides a way to detect a clone of the electronic device.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventor: Nikita Veshchikov
  • Patent number: 12196840
    Abstract: There is described a method of determining a time of arrival of a signal at a UWB ranging device comprising a first antenna, the signal being transmitted by another UWB ranging device, the method comprising: determining a first channel impulse response based on at least a part of the signal received at the first antenna; determining a first time value as an earliest point in time at which the amplitude of the first channel impulse response exhibits a peak value; setting a candidate time value to the first time value; determining a first upper value as the amplitude of the first channel impulse response at a time value corresponding to the candidate time value plus a predetermined upper time value; determining a second upper value as the peak value plus a predetermined upper amplitude value; determining a first lower value as the amplitude of the first channel impulse response at a time value corresponding to the candidate time value minus a predetermined lower time value; determining a second lower value as t
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventors: Dominik Doedlinger, Michael Schober, Christian Eisendle
  • Patent number: 12199333
    Abstract: A semiconductor device comprising a substrate, a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array having a uniform pitch, and a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array having a uniform pitch. The second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch. Also provided is a method of manufacturing a multi-package module and a method of providing package-to-package grounding.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventors: Antonius Hendrikus Jozef Kamphuis, Jan Willem Bergman, Marcellinus Johannes Maria Geurts, Mustafa Acar, Paul Mattheijssen, Rajesh Mandamparambil, Andrei-Alexandru Damian, Amar Ashok Mavinkurve
  • Patent number: 12197626
    Abstract: Securing protocol keys in a communication node comprises transferring a protocol access key stored in a secure enclave of a secure host platform to a secure key store in a communication platform via a secure transfer. The protocol access key which is plaintext is secure from access by a host processor of the secure host platform. A protocol key stored in the secure enclave is encrypted to an encrypted protocol key. The encrypted protocol key is transferred from the secure enclave to the communication platform over an unsecure bus. The encrypted protocol key is deciphered based on the protocol access key in the communication platform to form the protocol key. The protocol key which is plaintext is secured from access by the host processor, the communication controller, or both.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventor: Khurram Waheed
  • Patent number: 12197994
    Abstract: A security platform includes a security tag having a wireless communication circuitry configured to receive a user identification (ID) from an ID tag. After receiving the user ID, the security tag tracks the distance the security tag moves away from a predetermined point. The security tag then compares the determined distance to a predetermined distance threshold to determine whether the security tag is within a range. In response to the determined distance being greater than the predetermined distance threshold, the security tag determines that the security tag is outside of the range and activates an alarm. The alarm of the security tag continues to be active until a second user ID having appropriate access rights is received.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventor: Jonathan Iglesias
  • Patent number: 12196793
    Abstract: It is described an attenuation measurement device (100), comprising: i) a detector unit (110) having a coupling capacitance (120), and an input capacitance (130), wherein the detector unit (110) is configured to produce a detector output signal (112a,b) in reply to an input signal received at the coupling capacitance (120) and/or at the input capacitance (130); ii) a test unit (140), coupled to the detector unit (110), and configured to provide a test signal (141) with at least one known signal property as a first input signal to the coupling capacitance (120); iii) a calibration unit (150), coupled to the detector unit (110), and configured to provide a calibration signal (151) as a second input signal to the input capacitance (130); and iv) a control unit configured to a) determine a first detector output signal (112a) produced by the detector unit (110) in response to the test signal (141), b) identify a specific calibration signal (151) that yields a second detector output signal (112b) that is compara
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventors: Harish Kundur Subramaniyan, Erwin Johannes Gerardus Janssen, Xi Zhang
  • Patent number: 12196838
    Abstract: A method of determining a distance between a first device and a second device. The method comprises: performing an initial-ranging-operation, by exchanging two multi-frame ranging cycles between the first device and the second device, to calculate a clock ratio and a multi-frame-cycle-ToF. The method further comprises performing a plurality of single-message ranging cycles, wherein each single-message ranging cycle comprises: at a predetermined first-device-cycle-time after an earlier message is sent from the first device to the second device, the first device sending a single-ranging-message to the second device; determining a second-device-cycle-time as the time between the second device receiving the single-ranging-message and the earlier message being received by the second device; determining a current-message-ToF based on: the previous-message-ToF, the first-device-cycle-time, the clock ratio, and the second-device-cycle-time.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventors: Jacek Tyminski, Sandeep Mallya, Pradeep Kumar Aithagani
  • Patent number: 12196804
    Abstract: Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventors: Tarun Kumar Goyal, Nikila Krishnamoorthy
  • Patent number: 12198998
    Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventors: Kuan-Hsiang Mao, Che Ming Fang, Yufu Liu, Wen Hung Huang
  • Patent number: 12199696
    Abstract: One example discloses a first near-field device, including: a controller configured to establish a near-field communications link with a second near-field device; wherein the controller is configured to monitor a characteristic of the near-field communications link; wherein the controller is configured to select a first modulation encoding for transmitting a near-field signal if the characteristic is greater than a first characteristic threshold; and wherein the controller is configured to select a second modulation encoding for transmitting the near-field signal if the characteristic is less than the first characteristic threshold but greater than a second characteristic threshold.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: January 14, 2025
    Assignee: NXP B.V.
    Inventors: Liesbeth Gommé, Anthony Kerselaers