Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO? signals, and outputs a second controlled LO signal output to a sense circuit.

Abstract: A linear chirp radar system, apparatus and method use a radar control processing unit to control an LFM radar front end which generates analog-to-digital (ADC) sample signals from one or more target return signals received in response to transmitted linear chirp radar signals, where the radar control processing unit is connected and configured to mitigate range migration by directly filtering the ADC samples using a modified Doppler filter that is tuned to fast-time scaled, slow-time frequencies to generate a focused ADC Doppler cube, and by applying a Fourier Transform on each Doppler cell in the focused ADC Doppler cube to generate a focused range-Doppler cube.

Abstract: Five-side mold protection for semiconductor packages is described. In an illustrative, non-limiting embodiment, a semiconductor package may include: a substrate comprising a top surface, a bottom surface, and four sidewalls; an electrical component comprising a backside and a frontside, where the frontside of the electrical component is coupled to the top surface of the substrate; and a molding compound, where the molding compound encapsulates the backside of the electrical component and the four sidewalls of the substrate.

Abstract: A data processing system includes a rich execution environment, a hardware accelerator, a trusted execution environment, and a memory. The REE includes a processor configured to execute an application. A compute kernel is executed on the hardware accelerator and the compute kernel performs computations for the application. The TEE provides relatively higher security than the REE and includes an accelerator controller for controlling operation of the hardware accelerator. The memory has an unsecure portion coupled to the REE and to the TEE, and a secure portion coupled to only the TEE. The secure portion is relatively more secure than the unsecure portion. Data that is to be accessed and used by the hardware accelerator is stored in the secure portion of the memory. In another embodiment, a method is provided for securely executing an application is the data processing system.

Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a first antenna configured to receive and transmit a first set of near field communication (NFC) signals, wherein said first set of NFC signals relates to NFC transactions; a second antenna configured to receive and transmit a second set of NFC signals, wherein said second set of NFC signals relates to wireless charging operations; a controller; a first interface between the controller and the first and second antenna, the first interface comprising an antenna selection unit configured to select the first antenna or the second antenna in response to a selection signal received from said controller; a second interface between the controller and the first antenna; wherein the controller is configured to detect whether an external communication device is within communication range of the first antenna using the second interface.

Abstract: An electronic circuit is provided. The electronic circuit includes a full-bridge rectifier, a spurious tone detection circuit, and a controller. The rectifier circuit has a plurality of switching elements and first and second radio frequency (RF) terminals. The spurious tone detection circuit has a non-linear circuit element and is coupled between the first RF terminal and a first reference terminal. The spurious tone detection circuit provides a non-zero direct current (DC) voltage in response to detecting harmonic tones at the first RF terminal of the full-bridge rectifier circuit. The controller is coupled to the plurality of switching elements. The controller is for controlling the operation of the plurality of switching elements based at least in part on detecting the harmonic tones. In one embodiment, the electronic circuit may be a wireless charging receiver. In another embodiment, a method for detecting harmonic tones in the electronic device is provided.

Abstract: A mechanism is provided for estimating mounting orientation yaw and pitch of a radar sensor without need of prior knowledge or information from any other sensor on an automobile. Embodiments estimate the sensor heading (e.g., azimuth) due to movement of the automobile from radial relative velocities and azimuths of radar target detections. This can be performed at every system cycle, when a new radar detection occurs. Embodiments then can estimate the sensor mounting orientation (e.g., yaw) from multiple sensor heading estimations. For further accuracy, embodiments can also take into account target elevation measurements to either more accurately determine sensor azimuth and yaw or to also determine mounting pitch orientation.

Abstract: In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor formed in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.

Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Abstract: A Wilkinson power combiner (202) is described that includes: at least one input port (210) coupled to at least one output port (212, 214, 216, 218) by at least two power combining stages. A first power combining stage (204) of the at least two power combining stages is configured as a single-stage first frequency pass circuit and a second power combining stage (206) of the at least two stages is configured as a single-stage second frequency pass circuit, and wherein the first frequency is different to the second frequency.

Abstract: A method is provided for secure provisioning of a device. In the method, a plurality of integrated circuit (IC) devices is manufactured by a first entity for use in the device. The first entity provides signed provisioning software and stores in at least one provisioning IC device one or more keys used for provisioning the plurality of ICs. The provisioning device with the signed provisioning software is provided to a second entity. The second entity verifies the provisioning software using a stored key. The provisioning software encrypts provisioning assets provided by the second entity and provides the encrypted provisioning assets to the third entity. The signed provisioning software is provided to a third entity by the first entity. During manufacturing of the manufactured products by the third entity, the provisioning software verifies and decrypts the encrypted provisioning assets of the second entity to provision all the plurality of IC devices.

Abstract: A data processing system has a processor, a system memory, and a hypervisor. The system memory stores program code and data in a plurality of memory pages. The hypervisor controls SLAT (second level address translation) read, write, and execute access rights of the plurality of memory pages. A portion of the plurality of memory pages are classified as being in a secure enclave portion of the system memory and a portion is classified as being in an unsecure memory area. The portion of the memory pages classified in the secure enclave is encrypted and a hash is generated for each of the memory pages. During an access of a memory page, the hypervisor determines if the accessed memory page is in the secure enclave or in the unsecure memory area based on the hash. In another embodiment, a method for accessing a memory page in the secure enclave is provided.

Abstract: A vehicle radar system, apparatus and method use a radar control processing unit to generate a target response signal in at least a first dimension from compressed radar data signals and to perform cell-averaging constant false alarm rate (CA-CFAR) target detection by convolving the target response signal with a weighted kernel window signal in a frequency domain using a Fast Fourier Transform hardware accelerator, an element-wise multiplier, and an Inverse Fast Fourier Transform hardware accelerator to generate an output signal having a sign that indicates a target detection decision.

Abstract: A circuit includes a current mirror stage with a switch, that when made conductive, provides current between the input and the output of the current mirror stage through the switch. When the switch is nonconductive, current is not provided through the switch. The stage includes current mirror circuitry, that when the switch is nonconductive, provides current at the output that is mirrored from current provided to the input of the current mirror stage.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

Abstract: One example discloses a near-field communications device, including: a near-field antenna; a conformal material having a first surface and a second surface; wherein the first surface is dielectrically coupled to the antenna; and wherein the second surface is configured to be galvanically coupled to a host-structure.

Abstract: A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.

Abstract: Disclosed is a method of operating a low power wireless receiver in which a radio is periodically operable for receive intervals with sleep intervals therebetween and comprising a sleep clock having a sleep clock accuracy. A first transmission or packet is received. Based on a start moment of the first received packet, and an expected interval between packets, a nominal start moment is determined to start the radio for a packet window until a nominal end moment, for receiving a second packet; the packet window duration is extended in dependence on an estimated drift based on the SCA to provide a widened window. A start moment of a second received packet is measured within the widened window. An actual drift is calculated, from the start moment of the second packet; and an actual start moment and an actual window duration is determined, for receiving a third packet, based on the actual drift.

Abstract: In connection with an RF communication system, exemplary aspects involve a method for use in a communication system in which a first system (e.g., 802.11) that is asynchronously based and which is susceptible to interference from a second system (e.g., synchronous-based LTE-CV2X). Such interference is due to the frequency spectrum used by the first and second systems overlapping. To mitigate interference issues, example methods spreads out the times for messages in the first system, based on information concerning occupancy of the channel, and transmitting them relative to the end of a cycled transmission allocated for use by the second system.

Abstract: A package includes an integrated circuit, IC, die having circuitry configured to generate signalling for transmission to a waveguide and/or receive signalling from a waveguide via a launcher. The die is coupled to an interconnect layer extending out from a footprint of the die. The launcher is formed in a launcher-substrate, separate from the die. The launcher is coupled to the die to pass the signalling therebetween by a connection in the interconnect layer. The launcher includes a launcher element mounted in a first plane within the launcher-substrate and a waveguide-cavity including a ground plane arranged opposed to and spaced from the first plane. The waveguide-cavity is further defined by at least one side wall extending from the ground plane towards the first plane. The die and launcher are at least partially surrounded by mould material of the package.