Abstract: A node in a wireless mesh network determines that a threshold level of duplicate network protocol data units (PDUs) are received. Further, the node receives one or more network PDUs comprising respective segments of transport data in a transport PDU. The node relays a subset of the received one or more network PDUs comprising respective segments to one or more neighboring nodes. The subset is relayed based on determination that the node has received a threshold level of duplicate network PDUs.

Abstract: A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes etching a gate stack comprising a first nitride layer. The first nitride layer is on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack is oxidized to form a polysilicon layer from the silicon layer, and to form a second oxide layer on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer is formed conformingly covering the second oxide layer. A nitride etch-stop layer is formed conformingly covering the second nitride layer.

Abstract: A co-prime coded DDM MIMO radar system, apparatus, architecture, and method are provided with a reference signal generator (112) that produces a transmit reference signal; a plurality of DDM transmit modules (11) that produce, condition, and transmit a plurality of transmit signals over which each have a different co-prime encoded progressive phase offset from the transmit reference signal; a receiver module (12) that receives a target return signal reflected from the plurality of transmit signals by a target and generates a digital signal from the target return signal; and a radar control processing unit (20) configured to detect Doppler spectrum peaks in the digital signal, where the radar control processing unit comprises a Doppler disambiguation module (25) that is configured with a CPC decoder to associate each detected Doppler spectrum peak with a corresponding DDM transmit module, thereby generating a plurality of transmitter-associated Doppler spectrum peak detections.

Abstract: An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks, and a power gate control circuit configured to control power gating for each VM block of a plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates a supply voltage from each block of a selected subset of the plurality of VM blocks and allows a retention voltage to power each VM block of a remaining subset of the plurality of VM blocks outside the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block of the remaining subset.

Abstract: A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.

Abstract: Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.

Abstract: A data unit comprising bits to transmit over one or more frequency segments in a frequency range is obtained. An effective bandwidth in each frequency segment of the frequency range is determined, where the effective bandwidth excludes bandwidth of one or more punctured subchannels in a respective frequency segment. Bits are encoded based on the effective bandwidth of each frequency segment followed by parsing the encoded bits to one or more streams and parsing the encoded bits of a stream to the one or more frequency segments. The parsing of the encoded bits of the stream comprises allocating a first number of consecutive encoded bits to a first frequency segment and allocating a second number of consecutive encoded bits to a second frequency segment, wherein the first number and the second number are based on the effective bandwidth of the first frequency segment and the second frequency segment. The encoded bits are modulated and mapped to subcarriers for transmission.

Abstract: A fault recovery system including a fault controller is disclosed. The fault controller is coupled between a processor and an interconnect, and configured to receive a time-out signal that is indicative of a failure of the processor to execute a transaction after a fault is detected in the processor. The failure in the execution of the transaction results in queuing of the interconnect. Based on the time-out signal, the fault controller is further configured to generate and transmit a control signal to the processor to disconnect the processor from the interconnect. Further, the fault controller is configured to execute the transaction, and in turn, dequeue the interconnect. When the transaction is successfully executed, the fault controller is further configured to generate a status signal to reset the processor, thereby managing a fault recovery of the processor.

Abstract: A method, system, apparatus, and architecture are provided for generating a sound-enhanced sensing envelope. A plurality of sensors and one or more passive sound sensors of a vehicle are used to collect and process sensor data signals characterizing an exterior environment of the vehicle, thereby generating a sensing envelope around the vehicle using direct sensing data signals and a sound-enhanced sensing envelope around the vehicle using indirect sensing data signals. The sound-enhanced sensing envelope is used to evaluate advanced driver assistance system commands for the vehicle with respect to safety-related events identified by the indirect sensing data signals.

Abstract: A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A method of acquiring data, a computer program product for implementing the method, a system for acquiring data, and a vehicle including the system. The method includes determining one or more data types and virtual channels required for one or more applications. The method also includes allocating a plurality of circular buffers in memory according to the determined data type(s) and virtual channel(s). One or more of the circular buffers are allocated to safety data lines. The remaining circular buffers are allocated to functional data lines. The method further includes storing at least one functional data line in a circular buffer allocated to functional data lines according to a data type and virtual channel of the functional data line. The method also includes storing at least one safety data line in a circular buffer allocated to safety data lines.

Abstract: A method for initial position detection of an electric motor includes determining a delta voltage for each of three pairs of stator windings by sequentially energizing and deenergizing each pair. The delta voltage is measured through a non-energized stator winding connected to a center tap of each respective pair. A minimum delta voltage is determined from an absolute value of a minimum of the three delta voltages. The minimum delta voltage is associated with a remaining stator winding not included in the respective pair. The two delta voltages not associated with the minimum delta voltage are compared to determine the proximity of the remaining stator winding to one of a D-axis of a rotor of the electric motor and a Q-axis of the rotor.

Abstract: A conditional direct memory access (DMA) channel activation system for executing a complex data transfer in a system-on-chip, comprising: a look-up table constructed and arranged to store elements of an activation profile; and a trigger circuit that controls a DMA transaction according to the activation profile of the look-up table.

Abstract: A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels.

Abstract: A clock control system for a scan chain generates two clock signals. During a shift phase of a testing mode of the scan chain, one clock signal is an inverted version of the other clock signal. The clock control system provides the clock signal and the inverted clock signal to two different scan flip-flops of the scan chain, respectively. Each of the two scan flip-flops performs a flip-flop operation when the received clock signal transitions from a de-asserted state to an asserted state. Thus, the two flip-flop operations are mutually exclusive during the shift phase. As a result, a dynamic voltage drop across the scan chain during the shift phase is reduced.

Abstract: A voltage regulator comprising a reference current generator coupled between a supply terminal and a reference terminal and configured to provide a reference current that is independent of an operating range of a supply voltage; and a regulator stage comprising: a current terminal configured to receive the reference current; a NMOS transistor having: a gate coupled to the current terminal; a drain coupled to the supply terminal; and a source coupled to an output terminal; a voltage reference circuit for providing a regulated output voltage coupled between the output terminal and the reference terminal, the voltage reference circuit comprising an output resistor coupled in series with a conduction channel of an output bipolar transistor arranged in a diode-connected configuration; an input bipolar transistor having: a conduction channel coupled between the current terminal and the reference terminal; and a base terminal coupled to a base terminal of the output bipolar transistor.

Abstract: Systems, apparatuses and methods described herein provide a method for padding a signal extension of orthogonal frequency-division multiplexing (OFDM) symbols. A transceiver may obtain a plurality of data symbols for transmission, and determine that a number of information bits for a last symbol of the plurality of data symbols is not an integer value. A special padding rule may be applied to add padding bits to the last symbol. A number of coded bits for the last symbol may be determined when the number of information bits for the last symbol has changed, and the plurality of data symbols for data transmission may be encoded based on the determined number of coded bits for the last symbol.

Abstract: An early fusion network is provided that reduces network load and enables easier design of specialized ASIC edge processors through performing a portion of convolutional neural network layers at distributed edge and data-network processors prior to transmitting data to a centralized processor for fully-connected/deconvolutional neural networking processing. Embodiments can provide convolution and downsampling layer processing in association with the digital signal processors associated with edge sensors. Once the raw data is reduced to smaller feature maps through the convolution-downsampling process, this reduced data is transmitted to a central processor for further processing such as regression, classification, and segmentation, along with feature combination of the data from the sensors.

Abstract: Embodiments of a method and device for multi-link communications are disclosed. In an embodiment, a method of multi-link communications involves, at a multi-link STA device (STA MLD) that supports a first link, link1, and a second link, link2, receiving a beacon on link2, acquiring an updated critical operating parameter for link1 in response to the beacon received on link2, and operating link1 according to the acquired updated critical operating parameter.