Abstract: An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

Abstract: Evaluation board (EVB) assemblies or stacks utilized in tuning electronic modules are disclosed, as are methods for tuning such modules. In embodiments, the module testing assembly includes an EVB and an EVB baseplate. The EVB includes, in turn, an EVB through-port extending from a first EVB side to a second, opposing EVB side; and a module mount region on the first EVB side and extending about a periphery of the EVB through-port. The module mount region is shaped and sized to accommodate installation of a sample electronic module provided in a partially-completed, pre-encapsulated state fabricated in accordance with a separate thermal path electronic module design. A baseplate through-port combines with the EVB through-port to form a tuning access tunnel providing physical access to circuit components of the sample electronic module through the EVB baseplate from the second EVB side when the sample electronic module is installed on the module mount region.

Abstract: A capacitor includes an electrode implemented in an electrode well of a substrate. The electrode well has a net N-type dopant concentration. The capacitor includes an electrode implemented in a conductive structure located above the substrate. The electrodes are separated by a dielectric layer located between the electrodes. A first tub region having a net P-type conductivity dopant concentration is located below and laterally surrounds the electrode well and a second tub region having a net N-type conductivity dopant concentration is located below and laterally surrounds the first tub region and the electrode well.

Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.

Abstract: A method, system, and apparatus are provided for determining mechanical characteristics of an electric motor and mechanical load with a speed signal modulator, FOC current loop, sensor-less rotor speed estimator, and speed signal demodulator which are configured to provide a q-axis AC reference current, q-axis DC reference current, estimated maximum AC rotor speed, estimated DC rotor speed, estimated phase angle of the AC rotor speed component, and torque constant to a mechanical characteristics estimator which is configured to determine a plurality of load torque parameters for the electric motor and mechanical load which include a combined moment of inertia parameter, a combined static friction, and a combined viscous friction coefficient parameter.

Abstract: Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack. In addition, multiple FET stacks are implemented in parallel in at least some switch branches to improve settling time for the branch.

Abstract: A wireless charger includes a plurality of charging units for charging wirelessly chargeable devices. Each charging unit includes one or more transmit coils for producing a wireless charging signal. Each charging unit also includes a driver circuit for driving the one or more transmit coils. The driver circuit is switchable according to a charging PWM duty cycle of that charging unit. Each charging unit is operable to perform a Q factor measurement by injecting excitation energy into the one or more transmit coils of that charging unit to produce a free resonance signal, and measuring a decay rate of the free resonance signal. Each charging unit is operable to alter its charging PWM duty cycle during a time window in which another charging unit of the wireless charger is performing a Q factor measurement.

Abstract: A critical data path of an integrated circuit includes a flip flop configured to receive a data input and provide a latched data output. A monitoring circuit includes a delay generator configured to receive the data input and provide a plurality of delayed data outputs corresponding to delayed versions of the data input with increasing amounts of delay, a selector circuit configured to select one of the plurality of delayed outputs based on a programmable control value, and a shadow latch coupled to an output of the selector circuit and configured to latch a value at its input to provide as a latched shadow output. A comparator circuit provides a match error indicator based on a comparison between the first latched data output and the latched shadow output, and an error indicator is provided which indicates whether or not an impending failure of the critical data path is detected.

Abstract: A system, method, apparatus and electronic control unit are provided for centralized data collection at a single controller device (110) in a distributed service-oriented system (100) by applying one or more classifiers (102-104, 114) to a message traffic packet (1) received at the Ethernet switch (101) of the single controller device to selectively identify service update information from service-oriented traffic messages in the message traffic packet without generating additional message traffic packets on the network system bus, and by mirroring each message traffic packet (3) containing service update information to a processing element (111) in the single controller to identify and extract specified data from the identified service update information for storage in a centralized database which is updated as services publish new information on the network system bus.

Abstract: A method, system, and apparatus for applying dithering to waveforms in a transmitter such as a Bluetooth transmitter. A current waveform corresponding to a current bit of a bitstream is received where the current waveform has a nominal frequency deviation defined by a value of the current bit. Based on the determination that the current waveform and an immediately previous bit of the bitstream are associated with different bit values, a first dithered signal is output which is defined by a first frequency offset pseudorandomly selected from a first set of frequency offsets. A subsequent waveform to the current waveform is received corresponding to a subsequent bit of the bitstream. Based on the subsequent bit and the current bit being associated with bits of the same value, a second dithered signal is output which is defined by a second frequency offset pseudorandomly selected from a second set of frequency offsets.

Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method of wireless communications involves encoding bits in Extremely High Throughput (EHT) signaling fields of a packet corresponding to at least one of an Orthogonal Frequency-Division Multiple Access (OFDMA) mode, a non-OFDMA mode, and a Null Data Packet (NDP) mode, wherein EHT signaling fields include a Universal signal (U-SIG) field and an EHT signal (EHT-SIG) field, and transmitting the packet with encoded bits corresponding to at least one of the OFDMA mode, the non-OFDMA mode, and the NDP mode.

Abstract: A process identifier transition monitor captures and assesses activities associated with a microprocessor or a microcontroller. Monitoring and assessment is performed by detection of process identifier transitions, which may be driven by an occurrence of one or more activities, such as execution of application software, system hardware mechanisms, or processor-internal mechanisms. Process identifier transitions are assessed to determine whether such transitions were expected. If a detected process identifier transition was not expected, then a system alert may be transmitted or some other appropriate response taken within the system.

Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

Abstract: The disclosure relates to a radar system comprising multiple synchronized transceivers.

Abstract: Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.

Abstract: Embodiments of an apparatus and method are disclosed. In an embodiment, a method of multi-link communications involves at an access point (AP) multi-link device, allocating Association IDs (AIDs) to non-AP multi-link devices, including allocating one of the AIDs to each of the non-AP multi-link devices, and at the AP multi-link device, generating a first indication element for the AIDs to indicate a buffered data configuration at the AP multi-link device for the non-AP multi-link devices.

Abstract: Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.