Abstract: A vehicle radar system, apparatus and method use a radar control processing unit generate compressed radar data signals, to apply the compressed radar data signals in parallel as a three-dimensional matrix to a coherent integrator (which generates a two-dimensional matrix of coherently integrated image data) and a non-coherent integrator (which generates a two-dimensional matrix of non-coherently integrated image data), and to generate a constant false alarm rate (CFAR) threshold from the two-dimensional matrix of non-coherently integrated image data for application to the two-dimensional matrix of coherently integrated image data to detect one or more targets in the MIMO radar signal returns from sample values from the two-dimensional matrix of coherently integrated image data that exceed the CFAR threshold.

Abstract: In an embodiment, a System-on-Chip (SoC) may include: a plurality of core domains, and a memory coupled to the plurality of core domains through a hardware firewall, wherein the hardware firewall is configured to enforce an adaptive Deny-By-Default (DBD) access policy in response to an event. In another embodiment, a circuit, may include: an access control policy generator configured to produce an adaptive DBD policy, and a hardware firewall coupled to the access control policy generator, the hardware firewall configured to enforce the adaptive DBD policy. In yet another embodiment, a method may include: storing an indication of a first DBD configuration state, the first DBD configuration state usable to enforce a first DBD access control policy, and changing the stored indication to a second DBD configuration state, the second DBD configuration state usable to enforce a second DBD access control policy.

Abstract: A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes etching a gate stack comprising a first nitride layer. The first nitride layer is on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack is oxidized to form a polysilicon layer from the silicon layer, and to form a second oxide layer on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer is formed conformingly covering the second oxide layer. A nitride etch-stop layer is formed conformingly covering the second nitride layer.

Abstract: A method of processing received Packet Data Convergence Protocol (PDCP) data packets in a PDCP layer module of a telecommunications base station, includes receiving by the PDCP layer module a plurality of data packets, determining by an analysis module of the PDCP layer module a proportion of the data packets received out of sequence over a predetermined number of received data packets, setting an expiry time of a reordering timer of a buffering and reordering module of the PDCP layer module according to the proportion, and starting the reordering timer upon receiving an out of sequence data packet in which the out of sequence data packet is added to a reordering buffer of the buffering and reordering module. If the reordering timer reaches the expiry time, data packets are removed from the reordering buffer and transferred from the PDCP layer module to another layer module of the base station.

Abstract: A system on a chip allows external NorFlash memory sharing by multiple master devices. The system on a chip is configured to use an external NorFlash memory and includes a plurality of master devices and NorFlash virtualising circuity. The NorFlash virtualizing circuitry is configured to suspend a program operation or an erase operation being carried out on the external NorFlash memory, permit a read operation to be carried out on the NorFlash memory and then resume the suspended program operation or erase operation. Each master device of the plurality of master devices operates as a master to independently access the external NorFlash memory.

Abstract: A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal to produce a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is down-converted to an intermediate frequency signal and converted by a high-speed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.

Abstract: A mechanism is provided by which a radar image can be generated using mmWave transmissions from 5G-NR type base station antenna arrays. Base stations in 5G-NR use a beam searching sequence utilizing a defined synchronization signal burst (SSB) during their communication initialization with client devices. Embodiments utilize these SSB signals as a radar “chirp” to build a radar image of the base station surrounding in parallel with the typical 5G-NR communication initialization. Antennas on the base station can receive the reflected signals to define the radar image, in conjunction with correlation and time-management logic to properly associate received reflected signals with original transmitted signals. Such information can be processed by a synthetic aperture radar processing logic to form the radar image.

Abstract: A process that incorporates teachings of the subject disclosure may include, for example, providing a first silicon dioxide layer on the silicon substrate, depositing a modifier layer on the first silicon dioxide layer, depositing a second silicon dioxide layer on the modifier layer to form a multilayer initial oxide and annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide. The annealing causes diffusion of modifier species from the modifier layer into the first and second silicon dioxide layers and results in amorphous polysilicates. The first and second silicon dioxide layers have thicknesses that prevent the diffusion of the modifier species from reaching top and bottom interfaces of the annealed multilayer initial oxide. Other embodiments are disclosed.

Abstract: A circuit for converting a first voltage to a second voltage in a communication system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the communication system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.

Abstract: An asymmetrical processing system is provided. The processor has a vector unit comprised of one or more computational units coupled with a vector memory space and a scalar unit coupled with a data memory space and the vector memory space, the scalar unit accessing one or more memory locations within the vector memory space.

Abstract: Disclosed are various embodiments for improving the accuracy of a phase associated with the radar signal by identifying a spectral signature associated with a radio frequency (RF) impairment and performing digital predistortion to enhance the radar performance and to compensate for the impairment that causes offset or imbalance of the phase rotator output cause signal distortion or otherwise degrade of the phase of the signal. The self-calibrating mechanism of the present disclosure is configured to identify the impairments, determine a spectral signature associated with the impairment, and optimize the phase error through digital predistortion of the RF signal based at least in part on the spectral signature associated with the impairment.

Abstract: A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.

Abstract: A boot charge circuit for charging a boot capacitor of a switching power converter with upper and lower switches including pulse circuitry that provides a boot refresh pulse in response to a pulse control signal transitioning to an active state to turn on the lower switch for a duration of the boot refresh pulse, and gate circuitry that prevents activation of the upper switch until after completion of the boot refresh pulse in response to the transitioning of the pulse control signal. The boot refresh pulse has a negligible duration relative to each switching cycle yet sufficient to charge the boot capacitor to enable a driver to turn on the upper switch. A load monitor may be included to disable the pulse circuitry from providing the boot refresh pulse during higher load levels.

Abstract: Embodiments are disclosed that for synthetic aperture radar (SAR) systems and methods that process radar image data to generate radar images using vector processor engines, such as single-instruction-multiple-data (SIMD) processor engines. The vector processor engines can be further augmented with accelerators that vectorize element selection thereby expediting memory accesses required for interpolation operations performed by the vector processor engines.

Abstract: A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

Abstract: A pulse stretcher is disclosed comprising, a stretcher input (10) and a stretcher output (20); an asynchronous finite state machine; and a delay generator (40) having a delay input connected to the stretcher output, and a delay output connected to a second input of the FSM. The asynchronous FSM comprises: a first Muller C-element gate (250) having an output connected to the stretcher output, a second Muller C-element gate (260) having an output; and a combinatorial logic circuit (270) connected to the stretcher input, to first and second inputs of each of the first and second C-elements. The first and second Muller C-element gates are cross-coupled via the combinatorial logic, such that the respective outputs of the C-element gates are complementary and, in response to receiving the input pulse at the stretcher input, the output of the first Muller C-element gate provides a stretched version of the input pulse.

Abstract: A millimeter-wave wireless multiple antenna system (80) and method (100) are provided in which a UE (120) uses a multi-antenna subsystem (81) to identify a plurality of m strongest transmit beams (122) from the base station (110) based on power measurements of a plurality of synchronization signal blocks (SSBs) transmitted on a corresponding plurality of transmit beams by the base station (110), and to generate a composite uplink random access channel (RACH) preamble (123) that is sent (124) to the base station (110) to identify the plurality of m strongest transmit beams and relative weights for each of the plurality of m strongest transmit beams which are used by the base station (112) to generate an optimal downlink transmit beam for use in sending a RACH response to the UE (120).

Abstract: A memory address generator for generating an address of a location in a memory includes a first address input for receiving a first address having a location in the memory being accessed during a first memory access cycle, and a next address output configured to output a next address comprising a location in the memory to be accessed during a subsequent memory access cycle based on the current address and a memory address increment value The address increment unit includes a counter arrangement and a selector arrangement, wherein each counter of the counter arrangement is configured to provide an output signal at the output indicative of a maximum value being reached and the selector arrangement is configured to provide a candidate memory address increment value based on the output of the counter arrangement as the memory address increment value output by the address increment unit.

Abstract: A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.

Abstract: Various embodiments relate to a method performed by a first wireless device for bandwidth negotiation for frame exchange in a TXOP with a second wireless device, including: announcing by the first wireless device a channel puncture scheme indicating whether some 20 MHz channels covering a BSS operating bandwidth are punctured or not; transmitting a frame to the second wireless device indicating a bandwidth for the frame exchange; receiving a frame from the second wireless device indicating a negotiated bandwidth for the frame exchange; and exchanging frames with the second wireless device using the negotiated bandwidth.