Abstract: Embodiments of an apparatus and method are disclosed. In an embodiment, a method of enabling and disabling of links in the system a multi-link communications system comprises receiving, by a first multi-link device in the multi-link communications system, a status change information of a link in the multi-link communications system for the first multi-link device from an enabled status to a disabled status, and in response to the status change information, at least partially resetting, by the first multi-link device, parameters related to per-link operations for the link.

Abstract: The disclosure relates to a bandgap reference voltage circuit, in which an output reference voltage is stable with respect to temperature and other variations. Example embodiments include a bandgap reference voltage circuit comprising an output voltage circuit and a plurality, n, of offset amplifiers connected between first and second voltage rails, each of the plurality of offset amplifiers comprising a differential pair of transistors that together define an offset between an input voltage at an input and an output of the amplifier, the offset amplifiers being chained together and connected to the output voltage circuit that provides a bandgap reference voltage dependent on a sum of the offsets of the plurality of offset amplifiers.

Abstract: Embodiments of a device and a method for multi-link operations are disclosed. In an embodiment, a device includes a processor configured to perform a first backoff operation on a first link and a second backoff operation on a second link of a multi-link device (MLD) that has a non-simultaneous transmission and reception capability (NSTR MLD), and transmit a first Physical Layer Convergence Protocol (PLCP) Protocol Data Unit (PPDU) on the first link at a first start time after the first backoff operation and a second PPDU on the second link at a second start time after the second backoff operation.

Abstract: Embodiments of methods of communications, communications devices, and redrivers are disclosed. In an embodiment, a method of communications involves enabling a Loss of Signal (LOS) detector and a Low Frequency Periodic Signaling (LFPS) detector connected to a communications channel, using a digital logic circuit, combining an output of the LOS detector and an output of the LFPS detector to generate a combined LFPS output, and outputting the combined LFPS output and the output of the LOS detector to control data communications through the communications channel.

Abstract: One example discloses a multi-radio device, including: a controller configured to be coupled to a first radio that is configured to transmit a first signal, and a second radio that is configured to transmit a second signal; wherein the controller includes a detection element configured to detect a third signal generated in response to simultaneous transmission of the first and second signals; wherein the controller includes a decision element configured to modulate one or more information packets in the first and second signals in response to the third signal.

Abstract: A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.

Abstract: A WLAN AP includes an array of antennas, a transceiver and a processor. The transceiver is configured to transmit via the array of antennas downlink packets to WLAN STAs, and to receive uplink packets from the STAs. The processor is coupled to the transceiver and is configured to send a request to a plurality of the STAs to transmit a respective plurality of channel-sounding packets corresponding to the plurality of STAs, to receive the plurality of channel-sounding packets from the plurality of STAs in response to the request, to compute, based on the received plurality of channel-sounding packets, a beamforming matrix that defines subsequent transmission beams aimed toward at least a subset of the plurality of STAs, and to transmit one or more downlink data packets to one or more of the STAs via the array of antennas, in accordance with the beamforming matrix.

Abstract: Communications may be effected in a communications environment involving a plurality channels having disparate bandwidth and channel center frequency indexes. Communications are effected using first communications type with a first channel bandwidth and first channel center frequency index. Communications are also effected via a second communications type using a separate set of fields indicating a second channel bandwidth and a second channel center frequency index, the second channel bandwidth being different than the first channel bandwidth and the second channel center frequency index being different than the first channel center frequency index. The channel center frequency index and bandwidth communicated in each communication may utilize separate subfields.

Abstract: A system for providing an enhanced acknowledgement (ENH-ACK) frame is configured to receive an incoming packet transmitted by an external device, determine that an ENH-ACK response is required based on a MAC header of the incoming packet schedule transmission of the ENH-ACK frame to the external device in accordance with a standard turnaround time limit relative to receipt of the incoming packet, determine contents of one or more packet processed fields of the ENH-ACK frame and populate the one or more packet processed fields, and complete transmission of the ENH-ACK frame with the populated packet processed fields.

Abstract: Aspects of the subject disclosure may include a power splitter. The power splitter can include a first splitter branch having a first amplifier with passive components, a second splitter branch having a second amplifier with passive components. The first splitter branch is substantially electrically isolated from the second splitter branch by configuring the first and second splitter branches to have similar phase delays. Outputs of the power splitter can be electrically coupled to the multi-stage amplifier. The power splitter can be manufactured on a single semiconductor die or integrally formed on the same semiconductor die with other circuits such as the multi-stage amplifier. Other embodiments are disclosed.

Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.

Abstract: Embodiments of a method and an apparatus for multi-link data transmission are disclosed. In an embodiment, a method of multi-link communications involves at a first MLD that supports a first link, link1, and a second link, link2, transmitting a first frame during a first Transmission Opportunity (TXOP) on link1, and a second frame during a second TXOP on link2, simultaneously to a second MLD, receiving, at the first MLD, a first response frame to the first frame transmitted on link1 after a transmission end time of the first frame, identifying, at the first MLD, that a response frame to the second frame transmitted on link2 was not received after the transmission end time of the second frame, and transmitting, at the first MLD, a third frame on link1 and a fourth frame on link2 simultaneously, after receiving the first response frame on link1.

Abstract: A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

Abstract: Various embodiments relate to a system and method for joint sounding by a client with a master access point (AP) and a slave (AP), including: receiving a message from the master AP; applying network allocation vector (NAV) rules to update a NAV values, wherein the received message is treated as an intra-basic service set (BSS) message when the transmit address (TA) of the received message has a prespecified value; receiving a first trigger frame; and transmitting a first channel state information (CSI) to the master AP when the channel is idle based upon the updated NAV value in response to the trigger frame.

Abstract: An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

Abstract: Evaluation board (EVB) assemblies or stacks utilized in tuning electronic modules are disclosed, as are methods for tuning such modules. In embodiments, the module testing assembly includes an EVB and an EVB baseplate. The EVB includes, in turn, an EVB through-port extending from a first EVB side to a second, opposing EVB side; and a module mount region on the first EVB side and extending about a periphery of the EVB through-port. The module mount region is shaped and sized to accommodate installation of a sample electronic module provided in a partially-completed, pre-encapsulated state fabricated in accordance with a separate thermal path electronic module design. A baseplate through-port combines with the EVB through-port to form a tuning access tunnel providing physical access to circuit components of the sample electronic module through the EVB baseplate from the second EVB side when the sample electronic module is installed on the module mount region.

Abstract: A capacitor includes an electrode implemented in an electrode well of a substrate. The electrode well has a net N-type dopant concentration. The capacitor includes an electrode implemented in a conductive structure located above the substrate. The electrodes are separated by a dielectric layer located between the electrodes. A first tub region having a net P-type conductivity dopant concentration is located below and laterally surrounds the electrode well and a second tub region having a net N-type conductivity dopant concentration is located below and laterally surrounds the first tub region and the electrode well.

Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.