Abstract: A secure electronic apparatus and a method for determining that a secure electronic apparatus has been tampered with. The apparatus includes a memory and a plurality of sensors which each to receive an input signal and output a digital signal determined by the input signal and by a physical quantity sensed by the sensor (e.g. capacitance). A measurement routine includes applying a plurality of input signal values to the sensors and, for each input signal value, using the digital output signals of each sensor to determine a combined output result. The combined output results of the measurement routine are compared with a set of combined output results stored in the memory. A detected a difference between the combined output results of the measurement routine and the set of combined output results stored in the memory can be used to determine that the secure electronic apparatus has been tampered with.

Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Abstract: Various embodiments relate to a method of encoding data and a related device and non-transitory machine readable storage medium, including: determining a factor set, S, to be used for encoding the value, h, wherein the factor set includes a plurality of subsets that are associated with respective digit positions in the value, h; selecting a plurality of factors from the factor set, S; and computing a product of the plurality of factors to produce an encoded value. Various other embodiments relate to a method of encoding data and a related device and non-transitory machine readable storage medium, including: determining a factor set, S, and weight, w, to be used for encoding the value, h; selecting a set, T, of w factors from the factor set, S, to represent the value, h; and computing a product of the set, T, to produce an encoded value.

Abstract: In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.

Abstract: Embodiments include methods and devices for processing a digital composite signal generated at a first sampling rate. The signal includes at least first and second carrier-bands arranged to define a first inner gap between the carrier-bands. The first inner gap includes at least a first gap between the highest frequency of the first carrier-band and the lowest frequency of the second carrier-band. The digital composite signal has a predetermined instantaneous bandwidth that is lower than a sampling bandwidth. An outer gap located outside the instantaneous bandwidth and within the sampling bandwidth is determined. The first inner gap is reduced to define a second inner gap, where a width of the second inner gap is related to a width of the outer gap. The resulting folded digital composite signal is decimated to a second sampling rate lower than the first sampling rate thereby creating a decimated folded digital composite signal.

Abstract: A reference circuit includes a bandgap core circuit and a cascode amplifier. The bandgap core circuit includes a first bipolar junction transistor (BJT), a second BJT having a control electrode coupled to a control electrode of the first BJT, a first resistor coupled to the first BJT and the second BJT, and a second resistor coupled to the second BJT. The cascode amplifier circuit includes a first branch coupled to the first BJT and a second branch coupled to the second resistor.

Abstract: A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

Abstract: A method and system are provided for digitally controlling a switch mode power supply without using analog-to-digital converters by providing an SMPS output in feedback to first and second comparators along with upper and lower reference voltage thresholds to detect excursion counts at dedicated counters which identify how many times an SMPS output voltage exceeds the upper and lower reference voltage thresholds during each cycle of a fixed frequency PWM signal, where the excursion counts are evaluated with a non-linear multi-step digital control loop detection sequence to generate duty cycle adjustment instructions for controlling each duty cycle of the fixed frequency PWM signal.

Abstract: A sensor system includes first and second capacitive sensors. An excitation circuit, coupled with the sensors, applies an excitation voltage to each of the sensors. The excitation voltage is characterized by a first, second, and third excitation voltage components, wherein the second and third excitation voltage components have opposite polarities. A capacitance-to-voltage (C/V) converter, electrically coupled with the sensors, generates a differential-mode output signal in response to the first excitation voltage component applied to the sensors, and the C/V converter generates a common-mode output signal in response to the second and third excitation voltage components applied to the sensors.

Abstract: A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.

Abstract: According to a first aspect of the present disclosure, an NFC device is provided which comprises: a transceiver unit configured to establish a communication channel between the NFC device and a further NFC device, said further NFC device being external to the NFC device; a power management unit configured to detect an inactive communication state of said communication channel and to cause the transceiver unit to enter into a power management mode in response to a detection of said inactive communication state. According to a second aspect of the present disclosure, a corresponding method for managing power in an NFC device is conceived. According to a third aspect of the present disclosure, a corresponding computer program product is provided.

Abstract: Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. The first metal layer and the metal particle-containing layer are then arranged in a stacked relationship with a second metal layer such that the precursor layer is disposed between the first and second metal layers. A low temperature sintering process is then carried-out at a maximum process temperature less than a melt point of the metal particles to transform the precursor layer into a sintered bond layer joining the first and second metal layers in a sintered multilayer heat sink. In embodiments wherein the sintered multilayer heat sink is contained within a heat sink panel, singulation may be carried-out to separate the sintered multilayer heat sink from the other heat sinks within the panel.

Abstract: An electronic device includes mutual capacitance sensing circuitry for a capacitive touch pad. The touch pad has pairs of transmit and receive electrodes. The sensing circuitry intermittently charges and discharges the transmit electrode, and then measures corresponding voltage level changes at the receive electrode. A non-linear voltage-to-current converter is used to detect the voltage level changes, which allows for great sensitivity to mutual capacitance changes.

Abstract: A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel transistor formed in an isolated P-well and an N-channel transistor coupled in series with the P-channel transistor. Forming the P-channel transistor in the isolated P-well essentially eliminates a raised threshold voltage due to body effect.

Abstract: The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.

Abstract: A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.

Abstract: A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. Leads in a first subset of the leads alternate with leads in a second subset of the leads. The inner portion of the first subset of the leads is bent. The die pad, the inner portion of the leads, and only a first portion of the openings adjacent the inner portion of the leads are encapsulated. A second portion of the openings and the output portions of the leads form a dam bar for the encapsulating material.

Abstract: A unit (10; 11; 12; 13) used to control a segment liquid crystal display (15; 16). The segment liquid crystal display (15; 16) includes at least a backplane electrode (20) and at least a front plane electrode (25) both associated with a same segment of the segment liquid crystal display (15; 16). The unit (10; 11; 12; 13) includes a controller (30; 40; 50) in order to generate a pulse-width-modulated control signal (35) that has two voltage levels and a variable duty cycle. The unit (10; 1; 12; 13) further includes an integrator (60; 61) to integrate the pulse-width-modulated control signal (35) and to provide an integrated control signal (90) which has more than two discrete voltage levels corresponding to different variable duty cycle values.

Abstract: A capacitive position sensor system for determining the position of an object, in particular on a surface of a contactless smartcard, is provided. The object is positioned within a sensitive area of the capacitive position sensor system and changes the capacitance of capacitors being arranged underneath the object. The capacitive position sensor system comprises a set of sensing elements being arranged in the form of a column. Each sensing element includes a first capacitor having a first electrode and a second electrode and a second capacitor having a first electrode and a second electrode. A specific weighting factor is assigned to each capacitor. A control unit is adapted to determine the position of the object in one dimension by analyzing the results of a plurality of sensed voltage levels for the first capacitors and the second capacitors of a plurality of integration cycles.

Abstract: An RF amplifier includes a transistor, a shunt circuit, an envelope frequency termination circuit, and an extra lead. The shunt circuit is coupled between a transistor current carrying terminal and a ground reference node. The shunt circuit has a shunt inductive element and a shunt capacitor coupled in series, with an RF cold point node between the shunt inductive element and the shunt capacitor. The envelope frequency termination circuit is coupled between the RF cold point node and the ground reference node. The envelope frequency termination circuit has an envelope resistor, an envelope inductive element, and an envelope capacitor coupled in series. The extra lead is electrically coupled to the RF cold point node. The extra lead provides a lead inductance in parallel with an envelope inductance provided by the envelope inductive element. An additional shunt capacitor can be coupled between the extra lead and ground.