Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

Abstract: An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

Abstract: A controller for a switched mode power supply, wherein the controller is configured to be connected to a synchronous rectifier.

Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.

Abstract: In an RF transmitter, a digital predistortion circuit receives a sequence of input sample blocks, and performs a digital predistortion process to produce a predistorted output signal. The digital predistortion process includes selecting a set of predistortion coefficients for an input sample block from a plurality of different sets of predistortion coefficients. Each of the plurality of different sets of predistortion coefficients is associated with a different combination of one of a plurality of time slices within a radio frame and one of a plurality of power ranges. The selected set of predistortion coefficients is associated with a time slice within which the input sample block is positioned and a power range calculated for the input sample block based on block power statistics of the sample block. The process also includes applying the selected set of predistortion coefficients to the input sample block to produce the predistorted output signal.

Abstract: A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.

Abstract: A power converter and a method for controlling a power converter are disclosed. The method involves generating a common mode control signal and a differential mode control signal in response to a first error signal and a second error signal, wherein the first error signal is a function of the voltage/current at a first output of a dual output resonant converter and the second error signal is a function of the voltage/current at a second output of the dual output resonant converter. The method also involves adjusting the voltage/current at the first output of the dual output resonant converter and the voltage/current at the second output of the dual output resonant converter in response to the common mode control signal and the differential mode control signal.

Abstract: Disclosed is a method of controlling a USB Power Delivery System including determining whether at least a predetermined length of initial bits of a message is received, turning on a clock when the predetermined length is received, determining whether the message has stopped, starting a counter when the message has stopped, determining whether a count value of the counter has reached a predetermined value, and turning off the clock when the predetermined count value has been reached.

Abstract: A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.

Abstract: Various embodiments relate to a method and apparatus for a method for under sampling a RF carrier signal, the method including receiving, by an analog digital converter, the RF carrier signal, selecting, by a multiplexer, a clock signal which includes a first clock signal and a second clock signal which are phase shifted, receiving, by the ADC, the clock signal which has a frequency less that the frequency of the RF carrier signal, sampling, by the ADC, the RF carrier signal using the selected clock signal and demodulating, by a digital signal processor, the RF carrier signal into I channel data and Q channel data for I/Q demodulation.

Abstract: A method and apparatus for regulating a non-isolated high voltage converter applies a PWM signal to a power transistor that couples an input voltage to a floating ground node to charge an inductor and generate an output voltage which is measured with a first floating comparator to disable the PWM signal upon detecting a high threshold output voltage, the first floating comparator having inputs connected across first and second resistive elements to measure a voltage across a feedback resistor connected in series with a diode between the output voltage and a neutral ground reference. Subsequently, the output voltage is measured with a second floating comparator to enable the PWM signal upon detecting a low threshold output voltage, where the second floating comparator has inputs connected across the first and second resistive elements to measure the feedback voltage across the feedback resistor.

Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Abstract: A Near Field Communication (NFC) enabled device is disclosed. The NFC device includes an antenna. The NFC device also includes an impedance matching network, a carrier frequency generator to generate a carrier wave, a receiver for receiving a magnetic induction wave, a transmitter, a driver circuit configured to alter an impedance of an antenna network associated with the antenna between a first impedance and a second impedance and a control unit. The control unit is configured to derive a first phase difference between the received magnetic induction wave and an internal clock at the first impedance and a second phase difference between the received magnetic induction wave and the internal clock at the second impedance. The control unit is further configured to change a phase of the carrier wave based on a difference between the first phase difference and a second phase difference.

Abstract: A chopper amplifier and method of operation are described. The chopper amplifier comprises a first chopper arranged to modulate an input signal using a first chopper signal having a chopper frequency. An amplification stage has an input arranged to receive the chopped signal and an output, and supplies an amplified signal at the output. An output chopper is arranged to integrate the amplified signal using a second chopper signal having the chopper frequency to generate an amplified output signal. The amplification stage is further configured to filter the chopped signal to attenuate signal components having frequencies lower than the chopper frequency.

Abstract: A DC-DC power converter converts a DC input voltage at an input node into a DC output voltage at an output node. The converter has a main control loop that generates control signals used to control series-connected p-type and n-type switches that selectively connect an inductor to the input node or to ground while operating the converter in either a continuous-conduction mode (CCM) or a discontinuous-conduction mode (DCM). Zero-crossing detection (ZCD) circuitry detects when the inductor current reaches zero and generates a ZCD control signal used to control the n-type switch to inhibit negative inductor currents during the DCM mode. Overshoot-protection (OP) circuitry detects when the DC output voltage gets too high and generates an OP control signal used to control the n-type switch to inhibit overshoot conditions at the output node that can result from CCM-to-DCM mode transitions and from sudden reductions in output current loading.

Abstract: A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads and test pads coupled to the bond pads. A test pad region is formed on the wafer. The test pad region has probe pads and common electrical interconnects that selectively electrically couple each of the probe pads to a bond pad on each of the dies. The common electrical interconnects in the test pad region reduce the possibility of probe damage to the integrated circuits and allow the dies to be tested concurrently before being cut from the wafer.

Abstract: A non-volatile memory is arranged to have a plurality of sectors. Each sector of the plurality of sectors includes a plurality of record locations. A memory controller includes an erase counter, a failed sector flag, and a retired sector flag for each of the plurality of sectors. If a record location of a sector fails to program, another location in the sector is selected to be programmed. The failed sector flag is set if a predetermined number of selected record locations of the sector fails to program. If the failed sector flag is set for a particular sector twice, and an erase count is greater than a predetermined erase count, then the retired sector flag is set for the failed sector indicating the sector is to be permanently retired from use. A new sector of the plurality of sectors becomes the current active sector for record programming operations. The method for retiring a sector occurs dynamically, during operation of the non-volatile memory.

Abstract: Techniques for operating a power converter system that includes an LLC resonant converter and a non-inverting buckboost converter that is located in front of the LLC resonant converter are disclosed. In an embodiment, the output voltage of a non-inverting buckboost converter is regulated in response to the input voltage and the output voltage of an LLC resonant converter in order to maintain a desired ratio between the input voltage and the output voltage of the LLC resonant converter. For example, the ratio between the input voltage and the output voltage of the LLC resonant converter is controlled to a desired ratio that matches the turns ratio of the LLC resonant converter's transformer and that may also match (as a second order effect) the ratio of Lr to Lm.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

Abstract: This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.