Abstract: A predictive controller for an inductive DC-DC converter comprising a switchable inductor is described. The predictive controller includes a DC-DC controller configured to generate a plurality of switching phases to control the inductor current in the switchable inductor, the duration of the switching phases being determined from at least one of a reference inductor current value and a reference output voltage value. The predictive controller includes a supervisory controller coupled to the DC-DC controller and configured to set a reference inductor current value dependent on an expected change in load current and/or voltage of a load configured to be connected to the load terminal. The expected change in load current and/or voltage is determined from a predetermined load profile.

Abstract: An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.

Abstract: In an embodiment, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes a load modulation module, a current source coupled to the load modulation module, an interface to a resonant circuit, the interface coupled to the load modulation module and the current source, and an interface to a charge source, the interface coupled to the current source, wherein the load modulation module is configured to provide a signal for transmission by modifying the load through the load modulation module, and wherein the current source is configured to provide a signal for transmission by generating pulses of current.

Abstract: Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

Abstract: A control methodology and apparatus for an engine suitable for use in capacitor discharge ignition systems for internal combustion engines or brushless DC motors is provided, which make use of a simple logic block to determine for instance an ignition timing advance angle or duty cycle signal based on actual engine speed versus engine control parameter data stored in a table, which is a read-only memory, preferably configurable. To minimize memory space, a small number of values of engine control parameter versus engine speed are stored in the table and the logic block determines the required engine control signal for a measured value of engine speed by an interpolation process, preferably linear interpolation.

Abstract: Embodiments of a Doherty amplifier device are provided, where the device includes a main amplifier that produces a first RF signal with a variable first output power and a peaking amplifier that produces a second RF signal with a variable second output power equivalent to the first output power multiplied by a power ratio n greater than one; first and second RF signals combined in phase at a combining node; and a main output matching network (OMN), wherein the main OMN forms a portion of an equivalent main path transmission line having a characteristic impedance equivalent to (n+1)·?{square root over (Ropt·R0)}, wherein Ropt is a load impedance seen at the main amplifier intrinsic current generator plane during a full power condition of the Doherty amplifier device and (n+1)·R0 is a load impedance seen at the combining node during a back-off power condition of the Doherty amplifier device.

Abstract: According to embodiments there is provided a magneto-resistive sensor module. The sensor module may comprise: an integrated circuit; magneto-resistive sensor elements arranged as a bridge circuit monolithically integrated on the integrated circuit; and a stress buffer layer arranged between the integrated circuit and the magneto-resistive sensor element. There is also a provided a method of manufacturing the magneto-resistive sensor module.

Abstract: A wireless charging system has a transmitter and a receiver. The transmitter has (i) a TX coil that wirelessly transfers power to the receiver and (ii) TX circuitry that powers the TX coil and detects receiver removal by comparing TX input power and TX power loss. The TX circuitry can determine (1) TX input power as the product of sampled TX input current and voltage and (2) TX power loss using a mapping based on sampled TX coil current. When the receiver is present, the difference between TX input power and TX power loss has a first value and when the receiver is removed, the difference has a second, lesser value. The transmitter detects removal of the receiver by determining when the difference decreases below a specified threshold level. By frequently generating and analyzing the difference, the transmitter can quickly detect receiver removal and safely power down the TX coil.

Abstract: A circuit includes a first resistive element having a first terminal coupled to an input node to receive a negative voltage, a second resistive element having a first terminal coupled to a first power supply terminal, and a third resistive element having a first terminal coupled to the first power supply terminal. A first current mirror includes a first transistor coupled to a second terminal of the second resistive element and a second transistor coupled to a second terminal of the third resistive element and the first transistor, wherein the output node corresponds to the second terminal of the third resistive element. A second current mirror includes a third transistor coupled to the first transistor and a fourth transistor coupled to the second transistor, third transistor, and a second terminal of the first resistive element. The circuit converts the negative voltage to the positive proportion voltage.

Abstract: A system on chip (SoC) is connected to multiple off-chip devices, where the off-chip devices share IO pads of the SoC. A pin-mux circuit is used to facilitate the IO pad sharing. The pin-mux circuit can be addressed using just one control register and a decoder, which allows the IO pads to be easily and flexibly assigned. The decoder generates pin-mux control bits based on a configuration word stored in the control register. The pin-mux circuit assigns IO pads of the SoC to the off-chip devices. Device controllers of the SoC provide output bits to corresponding ones of the devices by way of the IO pads, and the devices provide input bits to the device controllers via the IO pads. Chip area is saved by using a register-decoder scheme, and set-up requires writing just the one control register.

Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.

Abstract: A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

Abstract: The present disclosure relates to an echo controller, for use with a microphone and a device comprising a loudspeaker, the echo controller comprising: a sensor with sensing capabilities configured to provide displacement-signalling representative of a displacement of a diaphragm of the loudspeaker, wherein the sensing capabilities of the sensor are isolated from an external environment of the device; and a cancellation block configured to determine a cancellation-signal based on the displacement-signalling; wherein the cancellation-signal is for adapting a received-signal provided by the microphone to determine an echo-cancelled-signal.

Abstract: A method of secure key generation includes writing a predetermined write pattern to a particular address of volatile memory, wherein the volatile memory includes bit lines; reading data from the particular address while applying a first set of operating variables to the volatile memory, subsequent to the writing; sensing a first plurality of timing mismatches during the reading, wherein sense amplifiers are coupled to the bit lines, each latch of a plurality of latches is coupled between a respective pair of sense amplifiers, and each latch is configured to output a data value that indicates a respective timing mismatch between outputs of the respective pair of sense amplifiers; and determining an entropy ratio for the particular address, wherein the entropy ratio is equivalent to a ratio of a first number of latches that output a first data value to a second number of latches that output a second data value.

Abstract: A system for providing a first voltage generated by a main supply and a second voltage generated by a battery to an integrated circuit (IC) includes supply-selection, control logic and switching circuits. The supply-selection circuit includes first, second, and third transistors. The switching circuit includes fourth and fifth transistors that supply the first and second voltages to the IC when switched on. The supply-selection circuit selects and provides the higher of the first and second voltages to body terminals of the fourth and fifth transistors for maintaining required body-bias voltage conditions. The control logic circuit generates a first control signal as long as the first voltage is within a predetermined range for keeping the fourth transistor switched on and a second control signal when the first voltage is not within the predetermined range for switching on the fifth transistor to supply the second voltage.

Abstract: Embodiments of a Doherty amplifier device are provided, where the device includes a main amplifier that produces a first RF signal with a variable first output power and a peaking amplifier that produces a second RF signal with a variable second output power equivalent to the first output power multiplied by a power ratio n greater than one; first and second RF signals combined in phase at a combining node; and a main output matching network (OMN), wherein the main OMN forms a portion of an equivalent main path transmission line having a characteristic impedance equivalent to ( n + 1 ) · Ropt · R ? ? 0 , wherein Ropt is a load impedance seen at the main amplifier intrinsic current generator plane during a full power condition of the Doherty amplifier device and R0 is a load impedance seen at the combining node during a back-off power condition of the Doherty amplifier device.

Abstract: A digital signal processor (DSP) includes a CPU, and a DMA controller. The DMA controller transfers data from a source to a destination as a function of an initialization command from the CPU. The DMA controller has a logic unit that performs filter operations and other arithmetic operations on-the-fly on a data stream transferred therethrough. The filter operations include multiplication by filter coefficients and addition, without processing by the CPU. The DMA controller may have subsets of hardware configurations that can perform different operations that are selectable as a function of the initialization command.

Abstract: A method of obfuscating a code is provided, wherein the method comprises performing a first level obfuscating technique on a code to generate a first obfuscated code, and performing a second level obfuscating technique on the first obfuscated code. In particular, the code may be a software code or a software module. Furthermore, the first level obfuscating technique and the second obfuscating may be different. In particular, the second level obfuscating technique may perform a deobfuscation.

Abstract: For an LED lighting application, overshoot-protection circuitry prevents an LED controller, such as a matrix lighting controller (MLC) that controls an array of LEDs, from falsely detecting an open-circuit condition in an LED controlled by the LED controller, by limiting the magnitude of an overshoot voltage (due to long-wire parasitic inductances) from occurring when a switch in the LED controller that is used to control the LED is turned off.