Abstract: A method performed by a radio base station, the method including determining that one of a Direct Memory Access (DMA) buffers of a communication link for a service provider has gone beyond a DMA buffer limit (empty or full), the communication link between a radio equipment control (REC) device and a radio equipment (RE) device that is operating based on a first bandwidth configuration of the communication link. The method further including in response to determining that the communication link is to change operation (due to reaching the DMA buffer limit) based on a second bandwidth configuration of the communication link, instead of the first bandwidth configuration, continuing operation of the communication link based on the second bandwidth configuration. The method further including that after going back under the DMA buffer limit, the communication link continuing operation based on the original first bandwidth configuration.

Abstract: The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.

Abstract: A unit (10; 11; 12; 13) used to control a segment liquid crystal display (15; 16). The segment liquid crystal display (15; 16) includes at least a backplane electrode (20) and at least a front plane electrode (25) both associated with a same segment of the segment liquid crystal display (15; 16). The unit (10; 11; 12; 13) includes a controller (30; 40; 50) in order to generate a pulse-width-modulated control signal (35) that has two voltage levels and a variable duty cycle. The unit (10; 1; 12; 13) further includes an integrator (60; 61) to integrate the pulse-width-modulated control signal (35) and to provide an integrated control signal (90) which has more than two discrete voltage levels corresponding to different variable duty cycle values.

Abstract: A capacitive position sensor system for determining the position of an object, in particular on a surface of a contactless smartcard, is provided. The object is positioned within a sensitive area of the capacitive position sensor system and changes the capacitance of capacitors being arranged underneath the object. The capacitive position sensor system comprises a set of sensing elements being arranged in the form of a column. Each sensing element includes a first capacitor having a first electrode and a second electrode and a second capacitor having a first electrode and a second electrode. A specific weighting factor is assigned to each capacitor. A control unit is adapted to determine the position of the object in one dimension by analyzing the results of a plurality of sensed voltage levels for the first capacitors and the second capacitors of a plurality of integration cycles.

Abstract: An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.

Abstract: An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN layer, resulting in a 2DEG in a contact region between the GaN layer and the second layer. The second layer has a relatively thin portion and a relatively thick portion. A third layer is formed over the relatively thick portion of the second layer. The third layer has a third bandgap that is different from the second bandgap, resulting in a 2DHG in a contact region between the second layer and the third layer. A transistor of a first conductivity type includes the 2DHG, the relatively thick portion of the second layer, and the third layer, and a transistor of a second conductivity type includes the 2DEG and the relatively thin portion of the second layer.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values to one intermediate value.

Abstract: There is disclosed a method of providing a software update to a secure element comprised in a host device, comprising converting the software update into a sequence of ciphertext blocks using a chained encryption scheme, and transmitting said sequence of ciphertext blocks to the host device. Furthermore, there is disclosed a method of installing a software update on a secure element comprised in a host device, comprising receiving, by the host device, a sequence of ciphertext blocks generated by a method of providing a software update of the kind set forth, converting said sequence of ciphertext blocks into the software update, and installing the software update on the secure element. Furthermore, corresponding computer program products and a corresponding host device are disclosed.

Abstract: Methods and a system are described for generating a waveform for transmitting data over a channel divided into a plurality of adjacent frequency subcarriers. One method includes receiving a plurality of data bits, each destined for a different receiver of a plurality of receivers. For each received data bit, the method further includes coding the data bit using a unique spreading code of a first set of spreading codes to generate a corresponding group of multiple copies of a data symbol. Additionally, the groups of data symbols, corresponding to the plurality of data bits, are interleaved to generate a sequence of interleaved data symbols, and the sequence of interleaved data symbols is mapped to the plurality of adjacent frequency subcarriers to generate a waveform symbol.

Abstract: A packaged RF amplifier device includes a transistor, a first input circuit, and a second input circuit. The first input circuit includes a first series inductance coupled between an input lead and a first node, a second series inductance coupled between the first node and the transistor's control terminal, and a first shunt capacitance coupled between the first node and a ground reference. The second input circuit includes a first shunt inductance and a second shunt capacitance coupled in series between the input lead and the ground reference. The first input circuit and the second input circuit create a fundamental frequency match for the device. The second series inductance and the first shunt capacitance present a short circuit to the ground reference for RF energy at a second harmonic frequency.

Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.

Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.

Abstract: An overvoltage protection circuit is disclosed. The overvoltage protection circuit includes an input voltage port, an output voltage port, a low pass filter coupled to the input voltage port and a voltage regulator coupled to the low pass filter. The overvoltage protection circuit also includes a transistor having a gate, a drain and a source. The transistor is coupled to the input voltage port and the output voltage port and the gate is coupled to the voltage regulator.

Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. The amplifiers described herein use a buffer that is implemented inside the device package. Specifically, the amplifiers can be implemented with a gate bias modulation buffer inside the device package, where the gate bias modulation buffer is configured to provide a modulated bias signal to a transistor gate of the amplifier.

Abstract: Disclosed is a controller for controlling a string of N LEDs connected in series and each having a current bypass switch in parallel therewith and configured to be supplied from a current source connected in series with the string of LEDs and being supplied by a supply voltage, the controller comprising: a respective bypass switch controller for each bypass switch and configured to control the respective bypass switch such that the respective LED has an on-period and an off-period, according to a common duty cycle; a phase control unit configured to set a respective timing of each of the bypass switches such that the fraction of LEDs not bypassed corresponds to the duty cycle; and a duty cycle adjustor configured to adjust the duty cycle, in dependence on the supply voltage. Associated methods and circuits are also disclosed.

Abstract: A transceiver circuit for operating in a controller area network (CAN), having a CAN bus network and a control unit, that supports a flexible data rate (CAN FD), is described. The transceiver circuit comprises: a transmit CAN path and a receive CAN path; an input node on the transmit CAN path; a detection module operably coupled to the input node on the transmit CAN path and arranged to receive an input frame from the control unit before the input frame is transmitted on the CAN bus network and determine whether the input frame on the transmit CAN path comprises a CAN FD frame; and at least one switching module, operably coupled to the detection module and coupleable to the CAN bus network, where the at least one switching module is operable to impart a first voltage value on the CAN bus network in response to the input frame being determined as comprising a CAN FD frame.

Abstract: Embodiments of an interconnect structure are provided, the interconnect structure including: a reference plane structure having a first major surface and a second major surface opposite the first major surface, the reference plane structure including a plurality of through holes from the first major surface to the second major surface; a plurality of conductive columns, each conductive column centered within a through hole; and a plurality of isolation structures, each isolation structure fills an annular region within the through hole between each conductive column and surrounding portion of the reference plane structure.

Abstract: A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value ?1, receive a second phase value ?2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value ?1, and compute a second digital phase shift control value based on the received second phase value ?2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.

Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.

Abstract: An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.