Abstract: A physically unclonable function (PUF) is implemented in a plurality of SRAM cells. In a method for generating a PUF response, a logic zero is first written to all the SRAM cells of the PUF. A bit line coupled to the storage node that stores the logic zero of each SRAM cell is biased to a predetermined voltage. The bit lines are then selected for an evaluation read operation. During the evaluation read, a read current of one of the bit lines from one column is converted to a first voltage and a read current of another bit line of another column is converted to a second voltage. The first voltage is then compared to the second voltage. A logic state of a bit of the PUF response is determined as a result of the comparison. The logic bit may be provided to the input of a parallel-in serial-out shift register. There may be a comparator for each logic bit, or a few comparators may be shared between the logic bits. The PUF response may be used to provide a signature for the data processing system.

Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.

Abstract: A method for processing an image, the method comprising retrieving an image, encoding the image as a string of components, deriving an exponent for each component, deriving mantissas wherein at least an approximation of each component can be derived from the exponents and mantissas, and wherein each exponent indicates the number of bits in its accompanying mantissa, compressing at least the exponents, and storing the exponents and the mantissas in a memory. There is also provided a apparatus for processing an image.

Abstract: A haptic feedback element controller for a mobile device and a method of controlling a haptic feedback element for a mobile device is described. The haptic feedback element includes a processor having a processor output, a first processor input, and a second processor input, a control state module having an output coupled to the second processor input and configured to determine at least one operating state parameter of at least one of a haptic feedback element and a haptic feedback element amplifier; wherein the processor is configured to alter the amplitude of one or more frequency components of an input signal received on the first processor input in dependence of the at least one operating state parameter and to output a processed signal to a haptic feedback element amplifier having an output for coupling to a haptic feedback element. The haptic feedback element controller may maximize the drive signal up to mechanical and thermal limits without lifetime reduction of the haptic feedback element.

Abstract: A speaker driver comprising an amplifier, configured to receive a test signal that comprises a plurality of equivalent test-blocks, and provide measurement-signalling for a speaker at the amplifier output. The measurement-signalling comprising a plurality of measurement-blocks, wherein each of the measurement-blocks corresponds to the output of the amplifier for one of the plurality of test-blocks. The speaker driver also includes an output-current-sensor configured to: measure a current level of the measurement-signalling, and provide sensed-signalling that comprises a plurality of sensed-blocks, wherein each of the plurality of sensed-blocks corresponds to one of the plurality of measurement-blocks of the measurement-signalling.

Abstract: Various embodiments relate to a device for generating code which implements modular exponentiation, the device including: a memory used to store a lookup table; and a processor in communication with the memory, the processor configured to: receive information for a generated randomized addition chain; output code for implementing the modular exponentiation which loads elements from the lookup table including intermediate results which utilize the information for a generated randomized addition chain; and output code for implementing the modular exponentiation which uses the loaded elements to compute the next element.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate within the doped isolation barrier, having the first conductivity type, and in which a channel is formed during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate. The plurality of RESURF layers are arranged in a stack between the body region and the doped isolation barrier. The plurality of RESURF layers include an upper layer having a second conductivity type, a lower layer having the second conductivity type, and an isolation coupling layer disposed between the upper and lower layers, in contact with the doped isolation barrier, and having the first conductivity type.

Abstract: A sensor system is disclosed. The sensor system includes a first sensor path comprising a first sensing element and a second sensing element being connected in series between a first supply terminal and a second supply terminal and an intermediate node connected in between the first supply terminal and the second supply terminal, a second sensor path comprising a third sensing element and a fourth sensing element connected in series between the first supply terminal and the second supply terminal, a first reference node connected in between the first supply terminal and the second supply terminal, and a second reference node connected in between the first supply terminal and the second supply terminal, and a processing unit to receive an input signal from the intermediate node, a first reference signal from the first reference node, and a second reference signal from the second reference node.

Abstract: A receiver-audio-device and a transmitter-audio-device. The receiver-audio-device comprises a receiver-ultrasound-receiver, configured to receive transmitter-ultrasound-signals representative of a request, from a transmitter-audio-device, for complementary audio resources; and a receiver-processor, configured to generate a complementary-audio-output-signal based on at least the transmitter-ultrasound-signals and to provide the complementary-audio-output-signal to a receiver-loudspeaker. The receiver-loudspeaker is configured to provide a complementary-audio-output based on the complementary-audio-output-signal. The transmitter-audio-device, comprising: a transmitter-ultrasound-transmitter, configured to provide transmitter-ultrasound-signals representative of a request for complementary audio resources; a transmitter processor, configured to generate an audio-output-signal and to provide the audio-output-signal to a transmitter-loudspeaker.

Abstract: A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

Abstract: A memory circuit includes plurality of bit-cells organized in a column, each bit-cell of the plurality is coupled to a first voltage supply terminal and a second voltage supply terminal. A word-line control circuit is coupled to each bit-cell of the plurality by way of a local bit-line. The word-line control circuit is configured to operatively couple the local bit-line with a global bit-line during a read operation. A first voltage generation circuit is coupled to the first voltage supply terminal. The first voltage generation circuit is configured to provide a first reduced voltage at the first voltage supply terminal during a first write operation. A second voltage generation circuit is coupled to the second voltage supply terminal. The second voltage generation circuit is configured to provide a second reduced voltage at the second voltage supply terminal during the first write operation.

Abstract: There is described a method of controlling application access to predetermined functions of a mobile device. The described method comprises (a) providing a set of keys, each key corresponding to one of the predetermined functions, (b) receiving an application from an application provider together with information identifying a set of needed functions, and (c) generating a signed application by signing the received application with each of the keys that correspond to one of the needed functions identified by the received information. There is also described a device for controlling application access and a system for controlling and authenticating application access. Furthermore, there is described a computer program and a computer program product.

Abstract: Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed.

Abstract: A method of managing wirelessly transmitted use-data in a wireless data transmission environment, the method comprising: Receiving the wirelessly transmitted use-data by a first receiver and estimating a reception quality of the use-data received by the first receiver by applying a quality criterion. In case the reception quality meets the quality criterion, the method moreover comprises using a second receiver for background scanning the wireless data transmission environment, and in case the reception quality does not meet the quality criterion, the method moreover comprises using the second receiver additionally for reception of the use-data, thus providing both receivers for a diversity reception of the use-data.

Abstract: A video processing system dynamically adjusts video processing prediction error reduction computations in accordance with the amount of motion represented in a set of image data and/or available memory resources to store compressed video data. In at least one embodiment, video processing system adjusts utilization of prediction error computational resources based on the size of a prediction error between a first set of image data, such as current set of image data being processed, and a reference set of image data relative to an amount of motion in a current set of image data. Additionally, in at least one embodiment, the video processing adjusts utilization of prediction error computation resources based upon a fullness level of a data buffer relative to the amount of motion in the current set of image data.

Abstract: Example near-field electromagnetic induction (NFEMI) antenna, including: an electric antenna having a first surface and a second surface; a magnetic antenna having a first, second and third coils; a first feeding connection coupled to one end of the first coil and the first surface; a second feeding connection coupled to another end of the first coil and coupled to one end of the second coil; wherein another end of the second coil is coupled to one end of the third coil; wherein another end of the third coil is coupled to the second surface; wherein the first, second and third coils are configured to carry a time varying current from the first and second feeding connections in a same direction; wherein the first and second coils are configured to have a first coupling coefficient; and wherein the first and third coils are configured to have a second coupling coefficient.

Abstract: The invention relates to radiofrequency transponder circuits, and in particular to such transponder circuits having a unique identifier. Embodiments disclosed include a radiofrequency transponder circuit (100) comprising an antenna module (101), a control circuit (103) and a memory (104), the transponder circuit (100) being configured to respond to a read command received via the antenna module (101) by the control circuit (103) reading and transmitting an identifier stored in the memory (104) via the antenna module (101), wherein the control circuit (103) is configured to perform an integrity check on data stored in the memory (104) upon being powered up by a reader field a first time via the antenna module (101) and to not perform the integrity check for a predetermined time period upon being powered up by a reader field subsequent times via the antenna module (101).

Abstract: A transmission gate circuit includes a pass gate and a control circuit and provides High Voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native NMOSFET in series with the pass gate provides overvoltage protection for additional circuitry. Well biasing, gate tracking and internal node clamping circuits ensure that all of the devices of the pass gate and control circuit operated within safe operational voltage levels. The two modes of operation can be selected by an enable signal. The transmission gate circuit can support up to a 5.5 volts input in a true open drain mode while an input/output supply voltage of 3.3 volts is supplied.

Abstract: The invention relates to a method of resetting a processor, the method comprising the receiving of a reset signal indicating that one or more parts of said processor need to be reset, and forwarding of said reset signal to said parts to be reset. The forwarding of the reset signal is delayed for a period of time for at least one of the parts to be reset. The clock frequency of at least one of the parts to be reset is gradually decreased during said period of time. In this way the total activity of the processor device is gradually decreased so as to avoid an on-chip voltage overshoot, which could cause a total reset of all the parts of the processor.

Abstract: An embodiment of a semiconductor die includes a base semiconductor substrate and an electrically conductive through substrate via (TSV) extending between the surfaces of the base semiconductor substrate. The bottom surface of the base semiconductor substrate includes a recessed region proximate to the TSV so that an end of the TSV protrudes from the bottom surface, and so that the TSV sidewall has an exposed portion at the protruding end of the TSV. Back metal, consisting of one or more metallic layers, is deposited on the bottom surface of the base semiconductor substrate and in contact with the TSV. The back metal can include a gold layer, a sintered metallic layer, and/or a plurality of other conductive layers. The die may be attached to a substrate using solder, another sintered metallic layer, or other materials.