Abstract: A time-synchronization apparatus and/or method involves identifying a frequency offset by implementing a frequency-offset-acquisition process which includes counting cycles of a local clock signal within a period of a reference pulse train. A phase offset of the local clock signal is determined, a residual frequency error is generated based on the phase offset, and at least one timer-adjustment signal that is based on the frequency offset and the residual frequency error is provided.

Abstract: A method is provided for detecting a profiling attack in an electronic device. The method includes causing provisioning of the device with a key and causing key operations using the key. A total key provisions counter value of a total key provisions counter is updated in response to the key provisioning. Also, a counter value of a total operations counter corresponding to a total number of operations is updated using the detected provisioned keys. A predetermined relationship between the total key provisions counter value and the total operations counter value is detected. An indication of the profiling attack is provided in response to the relationship meeting a predetermined criterion. In another embodiment, an electronic device having a total key provisions counter value and a total key operations counter value is provided. A predetermined relationship between the counter values indicates a profiling attack of the electronic device.

Abstract: A method to retrieve transaction address resulting in PCIe completion timeout includes monitoring a Peripheral Component Interconnect Express (PCIe) controller to detect a Completion Timeout (CTO) transmitted therefrom. A Master Identification (ID) of a Master and a transaction address of a transaction are stored in a configuration space, in response to detecting the CTO, wherein the transaction originates from the Master and the CTO is signaled in response to the transaction. The CTO is responded to with the Master identified by the Master ID in the configuration space.

Abstract: A communication system, including: a first modulator configured to modulate a first periodic signal with a first frequency based upon an input signal; a second modulator configured to modulate a second periodic signal with a second frequency based upon the input signal; an isolated differential channel including isolation capacitors with a first line connected to the first modulator and a second line connected to the second modulator; a mixer configured to mix signals received from the first line and the second line of the differential channel and to produce a mixer output signal; a bandpass filter connected to the mixer configured to filter the mixer output signal; an envelope detector configured to detect an envelope of the filtered mixer output signal; and a detector configured to detect a data signal in the envelope of the filtered mixer output signal and to produce an output signal.

Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a communication unit configured to execute a time-of-flight ranging session with an external communication counterpart; a clock offset measurement unit configured to measure a frequency offset of a device clock, wherein said device clock is configured to be used by the communication unit when said ranging session is executed; a processing unit configured to determine whether the measured frequency offset of the device clock has a predefined correlation with a frequency offset of a counterpart clock, wherein said counterpart clock is configured to be used by the external communication counterpart when said ranging session is executed. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.

Abstract: A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

Abstract: Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes. Test coverage data is generated for the circuit design including at least an identification of the one or more low test coverage areas.

Abstract: A network station scheduling a frame to be transmitted by a transmitter of the network station at a transmit time. The transmit time is based on a first clock. A request is then issued to a direct memory access (DMA) circuit to retrieve the frame from a system memory. An advance time offset associated with the first clock is determined based on an estimated DMA latency of the DMA circuit. A frame retrieved by the DMA circuit is provided to a staging circuit. When a time of a second clock reaches the transmit time of the frame in the staging circuit, the frame is transmitted at the transmit time. In an example, a time of the first clock is ahead of a time of the second clock by the advance time offset.

Abstract: Systems and methods for detection of persistent faults in processing units and memory have been described. In an illustrative, non-limiting embodiment, a Machine Learning (ML) processor includes one or more registers, and a data moving circuit coupled to the one or more registers. The data moving circuit can be configured to select, based upon a first value stored in the one or more registers, an original one of a plurality of parallel handling circuits within the ML processor to obtain an original data processing result. The data moving circuit can also be configured to select, based upon a second value stored in the one or more registers, an alternative one of the plurality of parallel handling circuits to obtain an alternative data processing result that, upon comparison with the original data processing result, provides an indication of a persistent fault in the ML processor.

Abstract: One example securely updates an integrated circuit to mitigate undesirable modifications and this involves an application circuit accessing an external network while a (e.g., nonvolatile) program memory is write protected; and a reset-boot circuit resetting and booting the application circuit while access to the external network is disabled, and causing an update for the application circuit. In response to an indication that an update is downloaded for installation, the downloaded update is installed in the memory while access to the external network is disabled, and execution of the reset mode is permitted after the update is installed. Also, a retrieval module may download, in response to an indication that an update is not downloaded, an update provided via the external network while the memory is write-protected and thereby permitting execution of the reset mode after the update is downloaded.

Abstract: A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.

Abstract: Oscillator circuitry and methods of operation thereof are provided in which the oscillator circuitry includes at least a first oscillator, a second oscillator, and a lock detector. The first oscillator is configured to generate a first clock signal. The second oscillator is configured to generate a second clock signal. The lock detector is configured to detect a stable phase lock between the first clock signal and the second clock signal and to switch an output of the oscillator circuitry from the first clock signal to the second clock signal in response to detecting the stable phase lock.

Abstract: The present disclosure relates to a Controller Area Network (CAN) system including: a CAN device and a monitoring device. The CAN device includes a transmit data (TXD) interface, a transmitter, a CAN BUS interface, and a control unit. The control unit reads out an identifier from a TXD message and compares the identifier with a reference tag. The CAN device generates a CAN BUS signal based on the TXD message at the CAN BUS interface. The control unit, if the comparison indicates that the identifier does not correspond to the reference tag, invalidates a representation of the TXD message by the CAN BUS signal and temporarily prevents another CAN BUS signal from being generated by the CAN device at the CAN BUS interface. The monitoring device receives an instruction message over a CAN BUS network and, in response, tests for reachability other CAN devices on the CAN BUS network.

Abstract: A bandgap reference circuit includes a first current generator having first and second bipolar transistors for generating a first current that varies proportionally as a function of temperature. A second current generator includes a field effect transistor for generating a second current that varies inversely as a function of temperature. A trimming circuit includes a third bipolar transistor sized to match the first bipolar transistor, a third current generator having a second field effect transistor coupled to a collector and base of the third bipolar transistor to generate a third current based on a base current of the third bipolar transistor, and a trim control circuit configured to modify the second current by adding the third current to or subtracting the third current from the second current based on a trim control signal. A bandgap reference current is generated by summing the first current and the modified second current.

Abstract: A system includes a reference field effect transistor (FET), wherein the reference FET is a depletion mode transistor, and a bias control circuit. The bias control circuit includes a voltage sensor connected to a drain terminal of the reference FET. The voltage sensor is configured to measure a voltage at the drain terminal of the reference FET as a measured voltage, determine a voltage difference between a reference voltage and the measured voltage, and output the voltage difference at a voltage sensor output terminal. The system includes a translation circuit connected the voltage sensor output terminal. The translation circuit is configured to convert the voltage difference into a negative gate bias voltage, and apply the negative gate bias voltage to a gate terminal of the reference FET.

Abstract: Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

Abstract: The present invention relates to a CAN module configured to be arranged between a CAN controller and a CAN transceiver. The CAN module received a TXD input signal from the CAN controller and is configured to transmit an TXD output signal to the CAN transceiver, wherein the TXD output signal is adapted by the CAN module to also comprising a test impulse. When monitoring the CAN BUS, the CAN transceiver will feed back an RDX signal to the CAN module and the CAN controller. The CAN module is configured to detect an error on the CAN transceiver or the CAN BUS depending on the transmitted test impulse and the test impulse received via the RDX signal. The present inventio also relates to a system comprising the CAN module and a method for the CAN module.

Abstract: Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.

Abstract: A system-on-chip (SoC) method and apparatus are disclosed for checking end-to-end integrity of communications over an network interconnect, where the SoC includes an initiator subsystem connected over the network interconnect to a target subsystem, wherein a first integrity module is configured to compute a first integrity value based on regular transaction messages sent or received by the initiator subsystem and to send a protecting information transaction (PIT) message over the network interconnect to the target subsystem, wherein a second integrity module is configured to compute a second integrity value based on regular transaction messages sent or received by the destination subsystem and to send a PIT response message over the network interconnect to the initiator subsystem, and wherein a compatibility module compares the first and second integrity values to verify the end-to-end integrity of the regular transaction messages sent or received over the network interconnect.

Abstract: A back-end-of-line integrated circuit interconnect device is formed on an integrated circuit structure having a first dielectric layer formed over a first conductive contact layer by forming an interconnect opening in the first dielectric layer which exposes at least a portion of the first conductive contact layer, filling the interconnect opening in the first dielectric layer with one or more polyimide layers in contact the first conductive contact layer; and applying a laser light source to directly convert the one or more polyimide layers to form a graphene interconnect structure in the first dielectric layer which is directly, electrically connected to the first conductive contact layer.