Abstract: A device includes an amplifier having an input terminal and an output terminal. The input terminal is configured to receive a radio frequency (RF) input signal. The device includes an output network coupled to the output terminal of the power amplifier and a first passively tunable integrated circuit (PTIC) coupled to the output network. The first PTIC includes a direct-current (DC) bias voltage input terminal configured to receive a fixed bias voltage, a control signal input terminal configured to receive a time-varying control signal, wherein the fixed bias voltage in combination with the time-varying control signal sets an operating reference point of the first PTIC, and an input terminal electrically connected to the output terminal of the amplifier, wherein a change in an output voltage signal generated by the power amplifier causes the first PTIC to modify a first effective impedance of a load presented to the power amplifier via the output network.

Abstract: The present invention relates to a CAN node being configured to predict, based on the at least one response message and a reference response, a fault of the CAN network and to determine a fault location of the predicted fault of the CAN network. The present disclosure also relates to a CAN system and a method for the CAN node.

Abstract: An integrated circuit includes an isolation test structure (ITS) formed in a non-active region. An electrical isolation between structures of the integrated circuit may be validated based on a measured resistance or conductivity across the ITS. In some embodiments the ITS includes interdigitated buffer layer structures. In some embodiments, the ITS is arranged in series with a test Through-substrate via (TSV). The test TSV is formed with a slower etch rate and smaller diameter than other standard TSVs of the integrated circuit and can be used to validate the formation of the standard TSVs based on measured resistance or conductivity thereof. By arranging the ITS and the test TSV in series, isolation of the integrated circuit and formation of TSVs in the integrated circuit can be validated using a single measurement.

Abstract: A device, a system, and a method for transmissions during a restricted Target Wake Time (rTWT) Service Period (SP) are disclosed. In an embodiment, the device includes a wireless network interface device implemented on one or more integrated circuits (ICs), where the wireless network interface device is configured to transmit a beacon on a first link that indicates an rTWT SP for the first link, transmit a frame prior to a wake period of the rTWT SP, where the frame is transmitted during a first Transmission Opportunity (TXOP) that overlaps with the wake period, and transmit low latency traffic on the first link during the wake period, where the first TXOP that overlaps with the wake period is at least one of ended and continued.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

Abstract: An integrated circuit comprising a package, phased antenna array and die. The die comprises a plurality of unit cells, wherein each unit cell is divided into quadrants. Each quadrant comprises a receiver terminal located on a first axis, and a transmitter terminal located on a second axis, wherein the first axis is orthogonal to the second axis, and there is mirror symmetry between the nearest neighbour quadrants in the unit cell. The package comprises a plurality of pairs of feed lines, each pair of feed lines comprising a receiver feed line and a transmitter feed line. The receiver feed line is connected to one of the receiver terminals and the transmitter feed line is connected to the transmitter terminal in the same die quadrant. The receiver feed line is orthogonal to the transmitter feed line. Each antenna element is coupled to a respective pair of feed lines.

Abstract: Embodiments of a method and a device of lockup detection for an eUSB repeater are described. In an embodiment, the method involves detecting received data at an analog receiver on a first side of the eUSB repeater, detecting an enable signal for an analog transmitter on a second side of the eUSB repeater, detecting an idle condition of the analog receiver on the first side of the eUSB repeater after detecting the enable signal, setting a timer, determining that the timer has elapsed, and resetting the eUSB repeater after the timer has elapsed while an idle condition is detected on the first side and the enable signal is detected on the second side of the eUSB repeater.

Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias.

Abstract: A method is provided for challenge-response authentication between a verifier and a prover. In the method, a challenge is received from the verifier, the challenge for verifying an identity of the prover. The challenge is computed using a first verifier key. The prover computes a response to the challenge using a first prover key. The prover also computes a delay time for delaying transmission of the response to the verifier using a second prover key and a delay computation function. The response is transmitted by the prover to the verifier at the computed delay time. The response is verifiable by the verifier using the first verifier key. An arrival time of the response is verifiable by the verifier using a second verifier key. In another embodiment, a device for providing a delayed response is provided.

Abstract: The present invention relates to a controller area network, CAN, transceiver comprising a monitoring unit configured to execute either a first process for detecting an error at the CAN signal lines or a different second process for detecting an error at the transceiver or the CAN signal lines depending on a mode of the CAN transceiver detected by the monitoring unit. The present invention also relates to a method for the CAN transceiver.

Abstract: A MEMS inertial sensor device, method of operation, and fabrication process are described wherein a MEMS inertial sensor and drive actuation units are coupled together in operational engagement, where the MEMS inertial sensor includes a substrate and a proof mass array positioned in spaced apart relationship above a surface of the substrate and constructed with a plurality of proof mass sub-structures which are each separately connected to the substrate with orthogonally disposed pairs of spring suspension structures and which are each rigidly connected to one or more adjacent proof mass sub-structures with one or more connector bars so that the plurality of proof mass sub-structures move as a single proof mass array that can operate at resonant frequencies of at least 100 kHz when oscillating in first and second orthogonal directions.

Abstract: An oscillator drive circuit and a trim circuit are implemented inside an integrated circuit of a sensor. The drive circuit provides an oscillating drive signal at a resonant frequency to drive a movable mass of the sensor. The drive circuit includes a phase shift circuit having an input for receiving a first signal indicative of an oscillation of the movable mass and having an output. The phase shift circuit adds a phase shift component to the first signal and produces a second signal shifted in phase by the phase shift component. The trim circuit includes a first comparator for receiving the first signal, a second comparator for receiving the second signal, and a processing element. The processing element determines a phase lag between the first and second signals and produces trim code for use by the phase shift circuit, the trim code being configured to adjust the phase shift component.

Abstract: The present disclosure relates to a transceiver (100) comprising a first and second terminal, a signal generation unit a signal generation unit (110) for generating a differential output voltage (Vout) between the terminals, a sensor unit (112) configured to measure an electric current (Iout) when flowing through one of the terminals, and a control unit (114) for controlling the signal generation unit, wherein the control unit is configured to control the signal generation unit during a calibration phase to generate a predetermined differential output voltage reference pattern (140), wherein the sensor unit is configured to measure a calibration current unit during the calibration phase, and wherein the control unit is configured to calibrate the signal generation unit depending on the calibration current. The present disclosure also relates to a method for the transceiver.

Abstract: A semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.

Abstract: A method and system comprises receiving a signal over an air interface. A binary sequence is detected in the signal. A legacy signal (L-SIG) field of a physical layer protocol data circuit (PPDU) is decoded based on the detected binary sequence and based on decoding the L-SIG field, two spoofing symbols which directly follow the L-SIG field is checked in the PPDU, wherein the two spoofing symbols comprise binary phase shift keying (BPSK) symbols. Based a presence of the two spoofing symbols, a long range portion of the PPDU is processed; and based on an absence of the two spoofing symbols, the PPDU is processed as a legacy PPDU.

Abstract: One example discloses a first multi-link device (MLD) within a wireless local area network (WLAN), including: a controller configured to receive a multi-link setup request for the first MLD to associate with a second MLD on a first set of PHY-layer links; wherein the controller is configured to transmit a response to the second MLD; and wherein the response associates the first MLD with the second MLD on a second set of PHY-layer links.

Abstract: A method is provided for radar ranging using an IR-UWB radar transceiver. The range is determined by measuring a time required by a transmitted pulse to be reflected by an object and returned to the transceiver. The method includes transmitting a ranging signal having a predetermined sequence of positive and negative pulses using a transmitter of the transceiver. A receiver of the transceiver receives a signal having a reflected portion and a feedthrough portion. In the method, the receiver cancels the feedthrough portion using a delayed pulse polarity signal such that when the delayed pulse polarity signal is multiplied and accumulated with the received signal, the feedthrough portion is canceled, and the reflected portion is amplified. In another embodiment, a transceiver is provided that cancels the feedthrough portion while amplifying the reflected portion. Cancelling the feedthrough portion allows short-range operation by removing a blind range of the transceiver.

Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

Abstract: One example discloses a wireless Access Point (AP) device, within a wireless local area network (WLAN), including: a controller configured to generate a reserve slot time trigger frame to a selected set of wireless devices; wherein the controller is configured to be coupled to an antenna; wherein the antenna is configured to transmit the reserve slot time trigger frame over a physical media to the selected set of user station devices (STAs) and exchange traffic with the selected set of STAs over the physical media; wherein the reserve slot time trigger frame is configured to reserve a slot time on the physical media; and wherein the controller is configured to transmit a burst of downlink (DL) traffic from the AP device during the slot time.

Abstract: An integrated circuit includes a first semiconductor device with an N type region biased by a first terminal and a second semiconductor device with a second region. An N type guard region is located laterally between the N type region of the first semiconductor device and the second region. A P type region is isolated in the N type guard region and is biased by a second terminal. The N type guard region is either electrically coupled to the second terminal through a resistor circuit or is characterized as floating.