Abstract: Wireless communications comprises generating a trigger frame which has a first set of bits which directly indicates a resource unit (RU) arranged as a distributed RU is solicited to be transmitted in an uplink direction in a first frequency block and a second set of bits which directly indicates for one or more second frequency subblocks a spreading bandwidth of tones of the distributed RU or whether a second frequency subblock is a punctured subchannel. An access point (AP) transmits the trigger frame in a downlink direction to a non-AP station. The non-AP station generates and transmits in the uplink direction a Physical Layer Protocol Data Unit (PPDU) to the AP station with data modulated on the tones of the distributed RU based on the first set of bits and the second set of bits of the trigger frame.

Abstract: A controller area network (CAN) node is described for determining a bus load on a CAN bus. An indication of a time window duration of a time window is received by the CAN node and a start time for determining a bus load and an end time based on the start time and the time window duration is defined. The bus load is based on determining whether the CAN bus is active for each bit of one or more bits detected on the CAN bus between the start time and the end time. The bus load is compared to a threshold range. A signal is sent to a host processor if the bus load exceeds or falls below the threshold range.

Abstract: A distributed radar system, apparatus, architecture, and method is provided for coherently combining physically distributed radars to jointly produce target scene information in a coherent fashion without sharing a common local oscillator (LO) reference by configuring a first (slave) radar to apply fast and slow time processing steps to target returns generated from a second (master) radar, to compute an estimated frequency offset and an estimated phase offset between the first and second radars based on information derived from the fast and slow time processing steps, and to apply the estimated frequency offset and estimated phase offset to generate a bi-static virtual array aperture at the first radar that is coherent in frequency and phase with a mono-static virtual array aperture generated at the second radar, thereby achieving better sensitivity, finer angular resolution, and low false detection rate.

Abstract: Aspects of the present disclosure are directed to communicating signals to receivers utilizing different protocols. As may be implemented in accordance with one or more embodiments, a set of signals are generated to include data configured in accordance with a first protocol and data configured in accordance with a second protocol. The set of signals are communicated over the wireless channel, by using the data corresponding to the first protocol for communicating with receivers operating in accordance with the first protocol and using the data corresponding to the second protocol to communicate with receivers operating in accordance with the second protocol.

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

Abstract: An amplifier device includes a first input terminal, a second input terminal, a first transistor having a first control electrode and first and second current-carrying electrodes, wherein the first control electrode is radio frequency (RF) coupled to the first input terminal and DC-coupled to a first bias network electrically coupled to the first control electrode, wherein the first bias network is configured to apply a first direct current (DC) bias to the first control electrode and is RF-isolated from the first control electrode. The amplifier device further includes a second transistor that includes a second control electrode that is RF coupled to the second input terminal and a second bias network electrically coupled to the second transistor, wherein the second bias network is configured to apply a second DC bias to the second transistor and is RF-isolated from the second transistor.

Abstract: A switchable termination resistance circuit for a transceiver physical layer interface.

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.

Abstract: A communication unit includes a plurality of cascaded devices that include at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device and at least one slave device each include: a demodulator circuit configured to receive a distributed reference clock signal and re-create a system clock signal therefrom; a clock generation circuit that includes an internally-generated reference phase locked loop configured to receive the re-created system clock signal to create a master-slave clock signal; and an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use a same master-slave clock signal to align respective sampling instants between each ADC of the at least one master device and at least one slave device.

Abstract: Embodiments of a power stage for a direct current (DC)-DC converter and a DC-DC converter are disclosed. In an embodiment, a power stage for a DC-DC converter includes an input terminal from which input power of the DC-DC converter with an input DC voltage is received, a high-side segment connected between the input DC voltage and an output signal of the power stage, and a low-side segment connected between the output signal of the power stage and ground. At least one of the high-side segment and the low-side segment includes stacked transistors having isolation terminals that are biased to reduce substrate injection.

Abstract: A mobile communication base station for joint communication and sensing and method of operation of a mobile communication base station is described. The mobile communication base station includes a baseband processor configurable to transmit and receive sensing and communication signals via one or channels. Each channel is configurable in one or more of a communications-transmit mode, a communications-receive mode, a sense-transmit mode and a sense-receive mode. For each channel, the baseband processor includes a carrier mapping-demapping module and a sense module. The baseband processor includes a controller coupled to the carrier mapping-demapping module and configured to control the carrier mapping-demapping module of the one or more channels to map the plurality of transmit-OFDM-symbols to a bandwidth part of an available OFDM bandwidth in the sense-transmit mode and the communications-transmit mode.

Abstract: An eUSB repeater is described for passing repeating mode packets between a differential bus and a single-ended bus. An eUSB transceiver is coupled to a single ended bus, a USB transceiver is coupled to a differential bus, and repeater logic is coupled to and between the eUSB transceiver and the USB transceiver. A first enable control circuit receives a digital state transition from the differential data bus and generates an enable signal to an analog single-ended transmitter of the eUSB transceiver. A second enable control circuit receives a digital state transition from the single-ended data bus and generates an enable signal to an analog differential transmitter of the USB transceiver.

Abstract: Aspects of the present disclosure are directed to radar transmissions and related componentry. As may be implemented in accordance with various embodiments, radar signals are generated and transmitted using both scanning and fixed beam analog signal codes concurrently/as combined for each radar signal. Reflections of the radar signals from a target are processed for ascertaining positional characteristics of the target.

Abstract: An electric motor controller having fault detection comprises: a driver circuit configured to drive an electric motor in response to a received speed demand signal; a measurement circuit configured to measure current through windings of the electric motor, the measurement circuit comprising a back emf, BEMF, observer configured to determine an estimated BEMF value, a BEMF error threshold and an estimated rotor angular speed value from the measured currents; a detector circuit configured to receive the rotor speed demand signal, the estimated BEMF value, the BEMF error threshold, the estimated rotor angular speed value and a measured rotor speed from a rotor speed sensor on the electric motor and to detect a fault in the electric motor controller if the estimated BEMF value lies outside the BEMF error threshold and the measured rotor speed is within a defined rotor speed error threshold.

Abstract: A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

Abstract: A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.

Abstract: A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

Abstract: An apparatus comprising an encoder is configured to: detect a first edge in the input signal and, in response, provide a pulse generation sequence comprising the encoder being configured to: generate, in the output signal, a first pulse, wherein the first pulse is provided over first and second minimum time periods irrespective of an edge subsequent the first edge being present in the input signal; and obtain a first sample of the input signal; and obtain a second sample at an end of the first pulse; and if the first sample and the second sample are indicative of different voltage levels, generate a second pulse; or if the first and second sample and the same maintain the voltage level in the output signal.

Abstract: An audio processor and method of audio processing for an amplifier system is described. The audio processor may receive an audio signal and adapt the audio signal generating a time varying offset. The time varying offset may be combined with the audio signal resulting in a shifted the audio signal level. The processed audio signal may also be clipped to remove the negative samples values. The processed signal may be used to drive an amplifier designed to only accept positive (or negative) signals such as a class C amplifier.

Abstract: Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module.