Patents Assigned to NXP
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Publication number: 20250096039Abstract: A back-end-of-line integrated circuit is formed on an integrated circuit structure having one or more polymer interlayer dielectric (ILD) layers formed over a first conductive wiring line layer by selectively processing an exposed portion of the one or more polymer ILD layers with application irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer.Type: ApplicationFiled: September 18, 2023Publication date: March 20, 2025Applicant: NXP USA, Inc.Inventor: Douglas Michael Reber
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Patent number: 12255700Abstract: A system includes a signal processing unit including an antenna configured to receive a radio frequency signal as a received radio frequency signal, and a baseband amplifier coupled to the antenna. The system includes a processor configured to cause the communication unit to stop generating a radio frequency polling signal, set an amplification gain of the baseband amplifier to a first gain value, periodically record, at a sample rate, an indication of a magnitude of the amplified radio frequency signal to generate a plurality of sample values, at a predetermined time interval after the communication unit stopped generating the radio frequency polling signal, set the amplification gain of the baseband amplifier to a second gain value, and transmit the plurality of sample values to a classifier module to determine whether the radio frequency signal is received from a near-field communication-enabled device.Type: GrantFiled: October 26, 2022Date of Patent: March 18, 2025Assignee: NXP B.V.Inventors: Mark Feichtinger, Johannes Stahl, Ulrich Andreas Muehlmann, Markus Wobak
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Patent number: 12255712Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: an ultra-wideband (UWB) communication unit configured to carry out UWB communication with an external communication device; a plurality of antennas operatively coupled to said UWB communication unit, at least one inertial sensor; an antenna selection unit configured to select, based on an output of the inertial sensor, a specific antenna of said plurality of antennas for carrying out the UWB communication. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.Type: GrantFiled: March 21, 2023Date of Patent: March 18, 2025Assignee: NXP B.V.Inventors: Filippo Casamassima, David Veit, Dorian Haslinger, Wolfgang Eber
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Publication number: 20250085344Abstract: Aspects of the subject disclosure may include, for example, monitoring first data to identify a first plurality of test points, analyzing the first plurality of test points to identify the first data as being associated with a first time domain included in a plurality of time domains, wherein respective portions of a device under test (DUT) are operative in accordance with a given time domain included in the plurality of time domains, and based on the analyzing of the first plurality of test points, generating first control signals to cause a first clock signal to be adapted to generate a second clock signal that is different from the first clock signal.Type: ApplicationFiled: November 1, 2023Publication date: March 13, 2025Applicant: NXP B.V.Inventors: CHANDAN GUPTA, SATISH CHANDRA TIWARI, ABHISHEK ASHOK BAJPAEE
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Publication number: 20250089359Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source/drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.Type: ApplicationFiled: September 11, 2023Publication date: March 13, 2025Applicant: NXP USA, Inc.Inventors: Mark Douglas Hall, Tushar Praful Merchant, Maryfe Hernandez, Anirban Roy
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Patent number: 12250711Abstract: Various embodiments relate to an access point (AP) configured to support a high priority (HP) service, including: a transceiver configured to: announce first enhanced distributed channel access (EDCA) parameters for a first device associated with the AP, wherein the first EDCA parameters support the HP service; announce second EDCA parameters for a second device associated with the AP that does not support the HP service; receive a HP priority access request frame from the first device configured to request HP services; determine that the second device supports the HP service through negotiation; and transmit an HP priority access response frame to the first device enabling HP traffic transmission by the first device.Type: GrantFiled: December 29, 2021Date of Patent: March 11, 2025Assignee: NXP USA, Inc.Inventors: Liwen Chu, Young Hoon Kwon, Hongyuan Zhang, Huiling Lou
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Patent number: 12250043Abstract: Various embodiments relate to a system and method for joint sounding by a client with a master access point (AP) and a slave (AP), including: receiving a message from the master AP; applying network allocation vector (NAV) rules to update a NAV values, wherein the received message is treated as an intra-basic service set (BSS) message when the transmit address (TA) of the received message has a prespecified value; receiving a first trigger frame; and transmitting a first channel state information (CSI) to the master AP when the channel is idle based upon the updated NAV value in response to the trigger frame.Type: GrantFiled: June 2, 2023Date of Patent: March 11, 2025Assignee: NXP USA, Inc.Inventors: Young Hoon Kwon, Liwen Chu, Sudhir Srinivasa, Hongyuan Zhang, Huiling Lou
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Patent number: 12248831Abstract: A smart card including a memory and a domain-specific language (DSL) interpreter is provided. The memory stores card data indicative of a real-time status of one or more attributes of the smart card. The smart card is linked to a service provider and card aggregator circuitry. The card data is stored in a format of the service provider and is updated each time a user of the smart card avails a service of the service provider using the smart card. Further, the DSL interpreter translates the card data to a format of the card aggregator circuitry based on a DSL script and provides the translated card data to the card aggregator circuitry. Based on the translated card data, the real-time status of the one or more attributes of the smart card is presented to the user by way of the card aggregator circuitry.Type: GrantFiled: April 24, 2023Date of Patent: March 11, 2025Assignee: NXP B.V.Inventors: Vinayak Gajanan, Elango Pandiyan Irulandy Gopalakrishnan, Maruthi Konda
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Patent number: 12248644Abstract: A circuit arrangement for a touch sensor includes a plurality of capacitive sensors, an ADC, a switch arrangement, and a controller. The capacitive sensors measure over a respective sampling period for detecting a touch event on a surface and provide an output. The ADC receives the output and determines a digital value over a conversion period. The switch arrangement selectively provides the output from the capacitive sensors to the ADC. The controller activates a first capacitive sensor to measure the capacitance for detecting a touch event, and activates a second capacitive sensor for detecting a touch event such that the respective sampling periods are at least partly concurrent. The controller also controls the switch arrangement to cause the ADC to receive the output of the first capacitive sensor after its sampling time and receive the output of the second capacitive sensor after its sampling time.Type: GrantFiled: July 6, 2023Date of Patent: March 11, 2025Assignee: NXP B.V.Inventor: Chao Wan
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Patent number: 12250570Abstract: Systems and methods for performing both wireless communications and wireless sensing in combination are disclosed herein. In one example embodiment, the system includes a base station (BS) including each of at least one antenna device including a first antenna device and at least one control unit. The control unit includes an input port coupled at least indirectly to the first antenna device, an output port, and a controllable circuit including each of a spillover cancellation circuit and a bypass circuit. The BS is configured to operate in each of a communication mode and a sensing mode. When the BS operates in the sensing mode, the spillover cancellation circuit of the controllable circuit is enabled and performs spillover cancellation. When the BS operates in a communication mode, the bypass circuit operates so that the spillover cancellation circuit is bypassed or otherwise does not affect how the output signal is generated.Type: GrantFiled: September 16, 2022Date of Patent: March 11, 2025Assignee: NXP B.V.Inventors: Cristian Pavao Moreira, Alphons Litjes, Alexander Vogt
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Patent number: 12250611Abstract: Described is a method for guiding a user for positioning a first RFID-enabled device relative to a second RFID-enabled device for allowing a robust RFID communication between the two RFID-enabled devices.Type: GrantFiled: August 8, 2022Date of Patent: March 11, 2025Assignee: NXP B.V.Inventors: Markus Wobak, Thomas Spiss, Abu Syed Firoz Ismail
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Patent number: 12249957Abstract: A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference VREF signal to a voltage feedback signal VFB, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal VFB for input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency fOUT by the trimming resistor.Type: GrantFiled: April 6, 2023Date of Patent: March 11, 2025Assignee: NXP USA, Inc.Inventors: Divya Tripathi, Sadique Mohammad Iqbal, Anubhav Srivastava, Krishna Thakur, Pragya Priya Malakar, John Pigott
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Patent number: 12249826Abstract: One example discloses a current limited power device, including: a switch; an output coupled to the switch; a sensor coupled to sense a voltage across a parasitic diode within the switch; and an output current limiter circuit coupled to reduce a output current (Iout) from the output of the power device if the voltage across the parasitic diode exceeds a threshold level.Type: GrantFiled: October 3, 2022Date of Patent: March 11, 2025Assignee: NXP USA, Inc.Inventor: Andrea Milanesi
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Patent number: 12250013Abstract: Systems and methods for digital predistortion (DPD) are disclosed herein. In an example embodiment, a digital front-end circuit includes a digital predistortion (DPD) block having a first input terminal and first output terminal, a PA having a second input terminal and second output terminal, and a transmitter coupling the first output terminal at least indirectly with the second input terminal. The DPD block is configured to receive a first input signal and to provide a first output signal having first and second components at the first output terminal. The DPD block includes a main distortion kernel that is configured to generate the first component, and a nonlinear memory kernel that is configured to generate the second component. The nonlinear memory kernel is configured to perform processing at least in part by a nonlinear envelope modulator including a linear finite impulse response (FIR) filter.Type: GrantFiled: September 27, 2023Date of Patent: March 11, 2025Assignee: NXP USA, Inc.Inventors: Mir Adeel Masood, Stephane Kerrurien, Peter Zahariev Rashev
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Patent number: 12242335Abstract: A fault indication from a fault source is to be provided to a demultiplexer which is configured to output the fault indication. The demultiplexer is configurable to output the fault indication to an OR gate of a plurality of OR gates coupled to a respective fault channel of a plurality of fault channels based on an application which uses the fault source as a resource. A reaction to the fault indication is performed based on the fault channel which received the fault indication.Type: GrantFiled: June 15, 2023Date of Patent: March 4, 2025Assignee: NXP B.V.Inventors: Aarul Jain, Hemant Nautiyal, Ashu Gupta
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Patent number: 12239434Abstract: One example discloses a near-field positioning device, including: an input interface configured to receive a set of body-parameters from a user; a controller configured to generate a set of recommended positions for a set of near-field wireless devices to be coupled to the user based on the body-parameters; and an output interface configured to output the recommended positions.Type: GrantFiled: July 9, 2021Date of Patent: March 4, 2025Assignee: NXP B.V.Inventors: Liesbeth Gommé, Anthony Kerselaers
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Patent number: 12241990Abstract: There is described a method of verifying a time-of-flight based ranging result in a UWB ranging device, the method comprising: exchanging a sequence of messages between the UWB ranging device and a further UWB ranging device as part of a double-sided ranging process to obtain round times and response times at both the UWB ranging device and the further UWB ranging device; estimating a time-of-flight value based on the round times and response times; and verifying the ranging result by performing a consistency check based on the estimated time-of-flight value and one or more predetermined parameter values. Furthermore, a UWB ranging device and a UWB ranging system are described.Type: GrantFiled: August 26, 2022Date of Patent: March 4, 2025Assignee: NXP B.V.Inventors: Wolfgang Küchler, Jacek Tyminski
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Patent number: 12244314Abstract: An apparatus includes a first transistor including a first gate, a first drain and a first source. A second transistor includes a second gate and a second source, the second gate is coupled to a first current source configured to generate a linear current ramp, the second source is coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source. A third transistor includes a third gate and a third source, the third gate is coupled to the first drain, and the third source is coupled to an inductive load, wherein the third transistor is configured to source a load current to the inductive load in response to an integration of the linear current ramp. A first capacitor is coupled between the third source and the second gate.Type: GrantFiled: September 6, 2022Date of Patent: March 4, 2025Assignee: NXP USA, Inc.Inventor: Thierry Michel Alain Sicard
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Patent number: 12244331Abstract: A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.Type: GrantFiled: July 20, 2022Date of Patent: March 4, 2025Assignee: NXP USA, Inc.Inventors: Kumar Abhishek, Srikanth Jagannathan, Frederic Benoist
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Patent number: 12243842Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and routing structure on a carrier substrate. At least a portion of the semiconductor die and routing structure are encapsulated with an encapsulant. A cavity formed in the encapsulant. A top portion of the routing structure is exposed through the cavity. A conductive trace is formed to interconnect the semiconductor die with the routing structure.Type: GrantFiled: December 8, 2021Date of Patent: March 4, 2025Assignee: NXP USA, Inc.Inventors: Michael B. Vincent, Scott M. Hayes