Abstract: A method of obscuring software code including a plurality of basic blocks wherein the basic blocks have an associated identifier (ID), including: determining, by a processor, for a first basic block first predecessor basic blocks, wherein first predecessor basic blocks jump to the first basic block and the first basic block jumps to a next basic block based upon a next basic block ID; producing, by the processor, a mask value based upon the IDs of first predecessor basic blocks, wherein the mask value identifies common bits of the IDs of the first predecessor basic blocks; and inserting, by the processor, an instruction in the first basic block to determine a next basic block ID based upon the mask value and an ID of one of the first predecessor basic blocks.

Abstract: A method of performing a cryptographic operation using a cryptographic implementation in a cryptographic system, including: receiving, by the cryptographic system, an identifying string value; receiving, by the cryptographic system, an input message; performing, by the cryptographic system, a keyed cryptographic operation mapping the input message into an output message wherein the output message is the correct result when the indentifying string value equals a binding string value

Abstract: A method of enforcing security settings in a cryptographic system, including: receiving, by the cryptographic system, a first input message associated with a first security setting of a plurality of security settings; performing, by the cryptographic system, a keyed cryptographic operation mapping the first input message into a first output message, wherein the keyed cryptographic operation produces a correct output message when the cryptographic system is authorized for the first security setting, wherein each of the plurality of security settings has an associated set of input messages wherein the sets of input messages do not overlap.

Abstract: In an embodiment, a method for performing forward error correction (FEC) on protected data packets is disclosed. The method involves creating a FEC table having columns for application data and columns for error-correction data (EC data). Then, a number of protected application data packets are received and placed in the FEC table. If an application data packet is received, then the application data from the packet is placed in the application data column. If an application data packet is not received, generated zeroes are placed in the application data column. Once the application data columns of the FEC table are full, EC data corresponding to the application data is received and placed in the EC data columns of the FEC table. The rows of the FEC table are then fed to the decoder for error correction.

Abstract: Embodiments of a method for forming a field emission diode for an electrostatic discharge device include forming a first electrode, a sacrificial layer, and a second electrode. The sacrificial layer separates the first and second electrodes. The method further includes forming a cavity between the first and second electrode by removing the sacrificial layer. The cavity separates the first and second electrodes. The method further includes depositing an electron emission material on at least one of the first and second electrodes through at least one access hole after formation of the first and second electrodes. The access hole is located remotely from a location of electron emission on the first and second electrode.

Abstract: A method of determining a fingerprint identification of a cryptographic implementation in a cryptographic system, including: receiving, by the cryptographic system, an input message that is a fingerprint identification message; performing, by the cryptographic system, a keyed cryptographic operation mapping the fingerprint identification message into an output message that includes a fingerprint identification; and outputting the output message.

Abstract: A method of authorization in a cryptographic system that provides separate authorization for a plurality of different input message groups using a single cryptographic key, including: receiving, by the cryptographic system, a first input message from a first input message group; performing, by the cryptographic system, a keyed cryptographic operation mapping the first input message into a first output message, wherein the keyed cryptographic operation produces a correct output message when the cryptographic system is authorized for the first input message group, wherein the keyed cryptographic operation does not produce a correct output when the cryptographic system is not authorized for the first input message group, and wherein each of the plurality of input message groups has an associated set of input messages wherein the sets of input messages do not overlap.

Abstract: A method of patching a cryptographic implementation without changing a key in a cryptographic system, including: sending a message from a first message set to the cryptographic implementation, wherein the first message uses a first portion of the cryptographic implementation; deciding to patch the cryptographic implementation; sending a second message from a second message set to the cryptographic implementation after deciding to patch the cryptographic implementation, wherein the second message use a second portion of the cryptographic implementation that is not used for any messages in the first message set.

Abstract: A method of gluing a cryptographic implementation of a cryptographic function to a surrounding program in a cryptographic system, including: receiving, by the cryptographic system, an input message; receiving a computed value from the surrounding program; performing, by the cryptographic system, a keyed cryptographic operation mapping the input message into an output message using the computed value from the surrounding program, wherein the output message is a correct output message when the computed value has a correct value; and outputting the output message.

Abstract: FM and AM receivers in car environments require a noise blanker circuit or method to reduce the audible disturbances generated by impulse noise, such as ignition noise, in the audio signal. The invention proposes a combination of time-domain and frequency-domain processing to reduce the audible distortion. The time-domain processing interpolates the signal during the impulse noise bursts, and the frequency-domain processing disperses the remaining signal distortion over time, or relocates it to positions in time where it is attenuated by a windowing technique.

Abstract: A processing unit for processing a multi-channel audio signal has a delay element (40) for delaying an FM sum signal (sum) and a converter arrangement (T) for converting an FM difference signal (diff) and a noise signal (diffnoise) to the frequency domain. Frequency-based noise suppression is used to derive a de-noised frequency-domain difference signal using a gain function which is limited to a maximal and a minimal value. This is then converted to the time domain, and the first and second audio signals are calculated from a delayed sum signal (sum2) and the de-noised time domain difference signal (diff2).

Abstract: Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.

Abstract: A voltage level translator includes an inverter circuit configured to switch an output of the inverter circuit between a first voltage level and a second voltage level. The voltage level translator also includes a capacitor connected to the output of the inverter circuit. The voltage level translator also includes a load connected to the capacitor. The capacitance of the capacitor is approximately 10 times larger than a capacitance of the load. An output signal of the voltage level translator has at least one of a different voltage swing and a different voltage domain than an input signal to the inverter circuit.

Abstract: A phased array transmitter is disclosed comprising a vector modulator, a true time delay block coupled to the vector modulator, a local oscillator phase shifter and RF-converter block coupled to the true time delay block, and an antenna. The vector modulator applies vector modulation to a baseband signal and provides an intermediate frequency signal to the true time delay block. The true time delay block applies a true time delay to the intermediate frequency signal and provides a delayed intermediate frequency signal to the local oscillator phase shifter and RF-converter block. The local oscillator phase shifter and RF-converter block multiplies the delayed intermediate frequency signal by a local oscillator signal and applies a phase shift to the delayed intermediate frequency signal to provide a radio frequency signal to the antenna for onwards transmission.

Abstract: An electronic device incorporating a randomized interconnection layer. In one example, the device includes a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern. In another example, a method of fabricating the device includes forming a set of electrodes proximate to a silicon substrate; depositing a heterogeneous layer of elements onto the substrate; etching the heterogeneous layer to form a randomized conductive pattern; and electrically coupling the electrodes to a sensing circuit and the randomized conductive pattern.

Abstract: A method of synchronising the reference clock of a first wireless device with a master reference clock of a second wireless device via a wireless network. The method involves transmitting, from the second wireless device to the first wireless device, a dedicated synchronisation frame via a dedicated synchronisation channel; receiving the dedicated synchronisation frame at the first wireless device; and synchronising the reference clock of the first wireless device with the master reference clock of the second wireless device based on the received dedicated synchronisation frame.

Abstract: A contactless smartcard type integrated circuit needing only two pins for performing a standard ATPG test is disclosed. A scan test may be performed using one pin for the clock and the other pin for the input and input of the scan test data. Additionally, security is enhanced by using an embedded signature generator to avoid observation of the data shifted out.

Abstract: A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.

Abstract: Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data to be stored on the non-volatile memory device; a first non-volatile memory block and a second non-volatile memory block, the first non-volatile memory block and the second non-volatile memory block being provided on a single die, wherein the first non-volatile memory block and second non-volatile memory block are of a different type such that the first non-volatile memory block and the second non-volatile memory block require incompatible external attack techniques in order to retrieve data there from; and—an encryption circuit for encrypting the external data forming encrypted data using unique data from at least the first non-volatile memory block as an encryption key, the encrypted data at least being stored into the second non-volatile memory block. The invention further relates to method of protecting data in a non-volatile memory device.