Abstract: Aspects of the present disclosure are directed towards apparatus useful for processing communications between different signaling voltage levels. Different signaling voltage levels are accomplished by creating true and complement signals from at least one input signal, each of which are subject to different delays, and level shifting the true and complement signals to a new signaling voltage level. The true or complement signal subject to a smaller timing delay is selected, and used to provide an output signal.

Abstract: Data carriers for inventorying by means of a communication station, whereby the communication station and each data carrier are brought into communicative connection, and each data carrier brought into communicative connection with the communication station is configured to generate a response signal that renders possible an inventorying of the data carrier and is capable of delivering a generated response signal with the use of a transmission start moment that can be selected from a plurality of transmission start moments, each data carrier tests whether another data carrier is already giving its response signal. Each data carrier is configured to discontinue the generation or delivery of its response signal if another data carrier is already providing its response signal.

Abstract: A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations.

Abstract: A microelectronic package assembly comprises a lead frame having a holding bar (16) and a microelectronic package (14). The microelectronic package (14) comprises a package body (22) and a connecting element (24) for connecting the package body (22) to the holding bar (16) of the lead frame (12). The connecting element (24) extends from an outer surface (26) of the package body (22) and is engaged with an ending part (28) of the holding bar (16).

Abstract: A current sensor, comprises an input conductor (IN) which is supplied with the current to be sensed and an output conductor (OUT) from which the current to be sensed is output. A conductor path is provided between the input conductor and the output conductor, wherein the path is provided on a first, movable element (1) and a second, fixed element (2). The path defines a pair of adjacent path portions (3,5; 3;4), one of the path portions (4;5) on the fixed element and the other (3) on one side of the movable element. An arrangement detects movement of the movable element to determine the current flowing. This arrangement uses a conductor path which can be part of the circuit being tested, and thereby does not require any additional components, other than the movement detector.

Abstract: The present invention relates to a data storage unit for a communication system node, a method for data storage and a communication system node. More particularly it relates to storing buffering data and control data in a unit located outside of a Communication Controller on system or host-controller level, wherein a time-triggered protocol runs on the node. By locating control and buffering related data, including format and behavior, outside the Communication Controller it becomes far more flexible, extendable, and re-configurable as data buffering related restrictions, e.g. buffer sizes and number of buffers, are moved from Communication Controller level to system level.

Abstract: The invention relates to an integrated circuit comprising a substrate having a first side and a second opposing side. An electronic circuit (EC) is provided at the first side (S1) of the substrate, wherein the electronic circuit (EC) comprises at least one magnetic field sensor (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit further comprises a magnetizable region (MR) provided on the second side (S1) of the substrate (SUB) by using a wafer-level type deposition processing step. The magnetic moment of the magnetizable region (MR) is configurable for generating a magnetic field (H1, H2) detectable at the location of the at least one magnetic field sensor (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit constitutes a very simple construction and enables a strongly miniaturized solution which is, because of its reduced dimensions well suitable for being used in bank cards. An attempt to remove the integrated circuit according to the invention from its environment (e.g.

Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.

Abstract: A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.

Abstract: A circuit for a switch mode power supply is presented. The circuit comprises a transient detection portion adapted to delay an analogue error signal (Vdiff) derived from the output voltage (Vout) of the switch mode power supply and to detect whether the difference between the output voltage and the delayed analogue error signal (Vdel) is within a predetermined range.

Abstract: A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals.

Abstract: Near field communication (NFC) devices may be required to operate at low power and so process small signals which are more susceptible to corruption by noise. An NFC device 100 is described having an antenna 10 which can be adapted to receive signal from a further NFC device. When a signal is received by the antenna, an input voltage is generated. A variable resistance element 12 is connected in series between the antenna 10 and an amplifier 14, which is adapted to increase the input resistance with increasing input voltage. By increasing the resistance when the input voltage is increased, the current drawn from the coil is reduced. This results in a lower overall power consumption of the device while maintaining reliable performance, because the higher input signal level is less susceptible to corruption by the noise generated by the variable resistance element 12, and the amplifier 14.

Abstract: A power supply regulator circuit uses a feedback loop to control current through a first output transistor from a power supply input to a regulated power supply output. The first output transistor is included in an integrated circuit. In order to avoid heating of the integrated circuit in excess of an acceptable level due to permanent supply of a high current through the first transistor, current through a second output transistor in parallel with the first transistor, but outside the integrated circuit is raised when it is detected that the current through the first output transistor exceeds a threshold level. The second output transistor outside the integrated circuit serves to take over supply of a part of the power supply current from first output transistor inside integrated circuit, when long term supply of that part from first output transistor would lead to undesirable heating of the integrated circuit. During a limited time interval a first transistor current above the threshold level is acceptable.

Abstract: The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR).

Abstract: The invention relates to a method of synchronizing the clock of different clusters including a first cluster (1) and a second cluster (2) which are connected by means of a connecting element (3) wherein the timing of the second cluster (2) is at least almost aligned to the timing of the first cluster (1), wherein the timing of the second cluster is determined by a node (4) of the second cluster which is connected to a reference node of the first cluster and wherein the node of the second cluster synchronizes itself with the reference node's timing and transfers an offset correction to the second cluster.

Abstract: An electrical power converter has a transformer (4) and detecting circuitry for deriving a reconstructed output or load current. In a first aspect of the invention the load current is computed by subtracting a scaled version of the time integral of the primary voltage (Vcap) from a scaled version of the primary current (Iprim). In a second aspect of the invention the load current is computed by subtracting a scaled version of the time integral of the voltage (Vaux) across an auxiliary winding (24) from a scaled version of the primary current (Iprim).

Abstract: There is disclosed an integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit. The management unit comprises: a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit; a data storage unit adapted to store information regarding the determined event occurrence; an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; and an output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis.

Abstract: An LED controller circuit for use in an LED drive circuit in which a coil current control scheme is used to deliver power to an LED arrangement from a phase cut dimmer. The controller circuit includes means for determining, based on an analysis/signal processing of the on-time of the transistor, the dimmer characteristics, including the on state and off states of the ac dimmed voltage signal. This avoids the need for the controller circuit to process the dimmer output.

Abstract: An integrated circuit device provides electrostatic discharge (ESD) protection, as may be applicable to circuits susceptible to ESD in conjunction with, or prior to, activation of a primary ESD circuit for dissipating an ESD. In connection with various example embodiments, primary and secondary ESD circuits discharge electrostatic pulses as may be present at a power input pad, with the secondary ESD circuit separated from the input pad by an impedance circuit. The secondary ESD circuit is configured to actively mitigate an electrostatic pulse present in conjunction with, or before, the activation of the primary ESD circuit, in response to an input voltage level achieving a threshold level. In some implementations, the secondary ESD circuit activates to mitigate some or all of the presentation of an electrostatic pulse to a circuit that competes with the primary ESD circuit, for drawing charge from a common node (e.g., a power supply pad).

Abstract: Infrared control signals are communicated between an infrared remote control unit (16) and an infrared controlled device (18) via network gateways (14). A sub-network of a backbone network (10) is automatically set up prior to transmission of messages. The sub-network comprises a selection of devices coupled to a backbone network (10). The setting up of the sub-network comprises automatically sending out a request from the first one of the network gateways (14) to detect network gateways (14) that indicate ability to transmit infrared control messages prior to transmission of the message and storing information defining the sub-network in the first one of the network gateways dependent to a response to the request.