Abstract: An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap.

Abstract: A magnetoresistive angular sensor and sensing method, in which an external magnetic field generator is used to provide a first mode in which a dc external magnetic field is provided in a predetermined direction and which dominates over the magnetic field generated by the input device being sensed. In a second mode, the external magnetic field is smaller. The angular sensor arrangement outputs from the two modes are combined, and this enables the input device angular orientation to be determined with offset voltage compensation.

Abstract: A voltage regulator is provided having one or more discharger circuits that compensate for low on-chip output capacitance and a slow loop response time. In one embodiment, the voltage regulator includes an output transistor coupled to an output voltage line, an output voltage sensing arrangement coupled to the output voltage line for producing an output feedback voltage, and an error amplifier coupled to the output feedback voltage, the output transistor, and a reference voltage for applying feedback control to the output transistor. A first discharger circuit is coupled to the output voltage line and to a reference potential, the first discharger circuit being triggered by a steep-rise overvoltage condition. In another embodiment, a combination of fast and slow discharger circuits is used to improve the load step response—i.e., to stop the output voltage from jumping too high and to pull it back to stable value very quickly, such that the load circuits are protected.

Abstract: A voltage sampling RF receiver in which an impedance control circuit controls the input impedance, by using a mixer stage which generates a feedback voltage, which is coupled to the RF input by a feedback resistor. A biasing arrangement can be used to adjust the feedback path so that local oscillator leakage signals are suppressed.

Abstract: A phase change memory cell has more than one memory region each being a narrowed region of phase change memory material extending between first and second electrodes. Each of the plurality of memory regions can be programmed to be in a low resistance state or a high resistance state by applying suitable programming conditions of current and/or voltage. The resistances of the high resistance states and the programming conditions to convert the high resistance states to the low resistance state are different in each of the plurality of memory regions.

Abstract: A varactor comprises a substrate having sets of gate units each having parallel gate strips. The gate units are located such that the gate strips of neighbouring gate units are oriented transverse to each other. An electrically conducting gate connection layer comprises gate connection units comprising parallel gate connection strips located over the gate strips, and a cathode connection frame around each of the gate connection units. A first electrically conductive anode layer comprises first layer anode strips located parallel to the gate connection strips and connected to alternate gate connection strips, and a first anode connection frame connected to the anode strips. A second electrically conductive anode layer comprises anode strips located parallel to the gate connection strips and connected to opposite alternate gate connection strips, and a second anode connection frame connected to the second layer anode strips.

Abstract: A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.

Abstract: A Power Factor Corrector (PFC), typically used as the first stage of switched mode power supplies, particularly suited for Universal Mains inputs, is disclosed, along with methods for controlling a switched mode power supply having power factor correction. In order to increase efficiency, particularly under low load conditions, without undue degradation of the Power Factor, the switching of the PFC circuit is confined to one or more operating windows within each half-cycle. In example embodiments, the operating window comprises a small time window centered around the peak of the mains voltage. The higher the power level, the wider the switching window.

Abstract: Consistent with embodiments of the present disclosure a redriver circuit is provided for a first and a second serial-unidirectional communications channel. The redriver circuit conditions received data signals by adjusting signal properties to correct for signal level attenuation and noise. The conditioned data signals are transmitted to corresponding outputs of the channels. The redriver circuit disables, in response to a first enable signal being inactive, current drawing circuitry of components for both channels on a common side of the redriver. The redriver circuit disables, in response to a second enable signal being inactive, current drawing circuitry of components for both channels on the other side of the redriver.

Abstract: A magnetoresistive angular sensing method is disclosed. In a first mode, a first dc external magnetic field in a predetermined direction is applied to an angular sensor arrangement in which the external magnetic field dominates over a magnetic field generated by an input device an angular position of which is to be sensed. In a second mode, a second external magnetic field is applied to the angular sensor. Outputs of the angular sensor arrangement in the two modes are processed to determine an angular orientation of the input device with offset voltage compensation.

Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.

Abstract: A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

Abstract: An antenna arrangement comprises a ground plane (14) and a planar antenna element (30) mounted spaced from and parallel to the ground plane. An open-ended slot (16) is provided in the ground plane (14), the slot being coextensive with an edge portion of the ground plane and having a first end (18) opening into the edge portion of the ground plane and a second closed end (20). An antenna feed (22) is coupled to the slot at a location intermediate the first and second ends. The planar antenna element is connected by an electrically conductive wall (28) to the edge portion of the ground plane, the wall (28) being coextensive with the slot (16). The combination of the slot shape, slot location and the wall serves to increase the bandwidth of the antenna arrangement.

Abstract: A secure computing device includes a secure cryptographic module with a key generation unit for generating a cryptographic key in dependence on received input. A storage is used for storing a virtual machine that is executable on a processor and at least one program that is executable on the virtual machine. A virtual machine manager including a unit 132 for determining an identifier associated 5 with the virtual machine, a unit 134 for supplying a representation of the identifier to the secure cryptographic module and retrieving a cryptographic keyfrom the secure cryptographic module; and a unit 136 for, under control of the cryptographic key, decrypting at least a part of data input to the processor and encrypting at least part of data output from the processor when the processor executes the virtual machine.

Abstract: A reader device (110) for reading information transmitted from a transponder (130) via a backscatter signal (132) generated by the transponder (130) in response to a stimulus signal (112) generated by the reader device (110), the reader device (110) comprising a first power estimation unit (114) adapted for estimating a first power value indicative of the power of the stimulus signal (112) at a position of the transponder (130) by evaluating a power information included in the backscatter signal (132), a second power estimation unit (116) adapted for estimating a second power value indicative of the power of the backscatter signal (132) at a position of the reader device (110), and a distance estimation unit (118) adapted for estimating a distance (d1) between the reader device (110) and the transponder (130) based on the first power value and the second power value.

Abstract: The invention relates to multi-channel audio signal processing, in particular to a method of processing a multi-channel audio signal and to a signal processing device.

Abstract: Power control is facilitated. In accordance with one or more embodiments, power is supplied to power rails of an integrated circuit using a power control circuit including a power regulator and a reset circuit that is responsive to a supply voltage. The power regulator provides power to the power rails, based upon a control signal. The reset circuit controls the power regulator to provide power to the power rails independently of the control signal when the supply voltage is below an operational voltage level, and controls the power regulator to provide power to the power rails in response to the control signal when the supply voltage reaches the operational voltage level.

Abstract: In a data carrier (1) for contactless communication with a base station (2) across an electromagnetic field (HF) generated by the base station (2), coil voltage control means (16) are arranged for controlling the unmodulated coil voltage (US) of the received signal (ES), the coil voltage control means (16) being arranged for control in response to an essentially decreasing coil voltage (US) when the field strength of the electromagnetic field (HF) increases.

Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.

Abstract: The invention relates to high power radiofrequency amplifiers, in particular to amplifiers having output impedance matching networks, exemplary embodiments of which include a radiofrequency amplifier having an active device mounted on a substrate within a device package, the amplifier having an output impedance matching network comprising a high pass network provided at least partly on the active device and a low pass network having a first inductive shunt connection between an output of the active device and a first output lead and a second inductive shunt connection between the output of the active device and a second output lead, wherein part of the second output lead forms an inductance contributing to the inductance of the low pass network.