Abstract: Power consumption of near-field communication devices is regulated by waking the device for communications when a potential external near-field device is detected, and by adjusting the resonant antenna circuit to account for the detected change in antenna environment. Such near-field communication devices include a resonant loop antenna circuit. The resonant loop antenna circuit is connected to an integrated circuit that includes a controller for controlling near-field communications via the resonant loop antenna circuit, an inductance detection circuit to detect changes in the antenna inductance, a wake-on circuit responsive to a sufficient change in antenna inductance to transition the controller from a low power sleep mode to a communications mode, and an antenna tuning circuit to adjust the variable component of the resonant loop antenna circuit to compensate for changes in antenna inductance and to maintain the target range of operation.

Abstract: A device has a micro electromechanical structure (10) with a first arm (102), at least one second arm (104a, b) connected to each other via a connection (100). Both arms (102, 104a, b) and the connection (100) are preferably made of a single crystalline body. The first and second arm (102, 104a, b) have end portions attached to a substrate, but otherwise the arms and their connection are free to move relative to the substrate. The first and second arm (102, 104a, b) extending from the end portions to the connection (100) along different directions, preferably perpendicularly to each other. An electrode (12) is provided on the substrate, adjacent to the micro electromechanical structure (10) to excite vibration of the structure. The two arms in different directions make it possible to reduce the nonlinearity of the stiffness during vibrations of the structure.

Abstract: The invention relates to a token, to an integrated circuit comprising the token, to a method of randomizing the token and a system for randomizing the token. The token comprises a physical unclonable function and comprising probing means for probing the physical unclonable function. The physical unclonable function comprises a capacitor comprising a dielectric medium being arranged at least partially between the electrodes of the capacitor. The dielectric medium is configured for contributing to a capacitance value of the capacitor and comprises conducting particles substantially randomly dispersed in the dielectric medium. The conducting particles comprise a phase changeable material being changeable between a first structural state having a first conductivity and a second structural state having a second conductivity different from the first conductivity.

Abstract: A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a sub-sampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively.

Abstract: A near field communication device being operable in a first operating state and a second operating state, the near field communication device comprising a communication unit adapted for communicating with an external device; and a control unit coupled to the communication unit; wherein the control unit is adapted for controlling the communication unit to be presented to the external device to be in the first operating state and supporting the second operating state, and wherein the control unit is adapted for switching the communication unit from the first operating state to the second operating state upon receipt of a configuration signal received from the external device.

Abstract: State definition and retention circuits are described. In one embodiment, a circuit includes two cross-connected PMOS transistors, first, second, and third NMOS transistors coupled to the PMOS transistors, an inverter circuit, and an output transistor connected to the PMOS transistors and to an output terminal of the circuit. The second NMOS transistor is connected to an input terminal of the circuit. A drain terminal and a gate terminal of the third NMOS transistor are connected to gate terminals of the PMOS transistors. The inverter circuit is coupled to the first and second NMOS transistors and to the input terminal. The inverter circuit is connected between a first power supply and a first base voltage. The PMOS transistors, the NMOS transistors, and the output transistor are connected between a second power supply and a second base voltage. Other embodiments are also described.

Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) power switching circuit and a method for operating a CMOS power switching circuit are described. In one embodiment, a CMOS power switching circuit includes a voltage selection circuit configured to output the highest output voltage between an output voltage of a primary power supply and an output voltage of a backup power supply and a control circuit configured to connect a load circuit to either the primary power supply or the backup power supply by comparing the output voltage of the primary power supply with a power supply switchover level that is set as a function of the highest output voltage. The backup power supply serves as a voltage reference to set the power supply switchover level only when the output voltage of the primary power supply is lower than the output voltage of the backup power supply. Other embodiments are also described.

Abstract: A bleeder arrangement for a phase-cut circuit for a high-impedance load and having a leading-edge phase-cut device is disclosed, the bleeder arrangement comprising: a controllable current sink adapted to sink a latching current through the leading-edge phase-cut device, and a controller for controlling the controllable current sink, wherein the controller is configured to disable the current sink after the leading-edge phase phase-cut device has latched in at least two stages. A controller for use in such an arrangement is also disclosed, as is a method of controller such a bleeder arrangement.

Abstract: Communication networks are implemented using a variety of devices and methods. In a particular embodiment for use in a communication network having RF-communication devices that communicate using a RF protocol, an RF-communication device is implemented with an RF transceiver (110) to communicate over the network using the RF protocol and being controllable in a reduced power-consumption mode in which the RF transceiver does not communicate over the network. The device also includes an RF receiver (104, 106) including an envelope detector (104) and a pulse generator circuit (106). The envelope detector circuit (104) providing an envelope-based signal to a pulse generator circuit (106) that, in response to the envelope-based signal and after generating a number of pulses that exceeds a predetermined number of pulses, prompts the RF transceiver (110) to transition out of the reduced power-consumption mode.

Abstract: A program is obfuscated by reordering its instructions. Original instruction addresses are mapped to target addresses. A cache efficient obfuscated program is realized by restricting target addresses of a sequence of instructions to a limited set of the disjoint ranges (33a-d) of target addresses, which are at lease half filled with instructions. Mapped address steps (34) are provided between the target addresses to which successive ones of the original instruction addresses are mapped. The address steps (34) include first address steps within at least a first one of the mutually disjoint ranges (33a-d). Between said first address steps, second address steps within at least a second one of the mutually disjoint ranges (33a-d). Thus, a deviation from successive addresses for logically successive instructions is realized.

Abstract: An authentication system includes a plurality of electronic tags (120, 122, 124) that are each associated with a respective unique identity ID. The tags include a memory (220) with a first memory location (222) for storing a pre-computed challenge and a second memory location (224) for storing a pre-computed response that is associated with the challenge. The first memory location (222) is non-readable from outside the tag. An access circuit (210) only provides the response after having received a challenge that matches the challenge stored in the first memory location. A reader station (110) obtains the identity associated with a tag. It then determines a corresponding challenge and sends the challenge to the tag. It receives a response from the tag and verifies the authenticity of the tag by comparing the received response to a response that corresponds to the challenge.

Abstract: In an example embodiment, there is method for assembling semiconductor devices, the method comprises providing a temporary carrier having a plurality device die locations and a boundary edge. Surrounding the device die locations, electrical connection pads are applied. Device die in the plurality of device die locations are mounted; the device die have pad landings electrically coupled to active components with the device die. The pad landings of the device die are wire bonded to corresponding electrical connection pads. With the molding compound flowing to the boundary edge of the temporary carrier, the device die are encapsulated. In a particular example embodiment, the electrical connection pads may be ball bonds.

Abstract: Embodiments of a method for operating a computer system are disclosed. In one embodiment, the memory unit has a non-volatile memory array and processing logic and the non-volatile memory array stores initialization data that is used by the processing logic to perform input/output operations of the memory unit. The method involves storing the initialization data in retention registers within the memory unit, wherein the retention registers are separate from the non-volatile memory array and retain data while the memory unit is power gated, using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating.

Abstract: The invention provides a transmitter comprising two (or more) phase locked loops controlling respective oscillators, and implementing different phase modulation. Multiple phases are derived from the respective oscillators, and an edge rotator forms an output signal from a combination of the phases. The oscillators can operate at different frequencies, neither of which is an integer multiple of the other, whereas the output signals of the multiplexers of the first and second phase locked loops are closer in frequency and can be the same. This reduces the problem of pulling, with a circuit that can be implemented with low power and area and with the versatility of being digitally intensive.

Abstract: A power factor correction stage comprising: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a first converter stage and one or more further converter stages, wherein each of the converter stages is connected to the input terminal and the output terminal, and each converter stage comprises a switch; and a controller configured to operate the switches of the converter stages. The controller is configured to operate the switch of the one or more further converter stages at a period of time after operation of the switch of the first converter stage for a current switching cycle, wherein the period of time corresponds to a proportion of the switching frequency for an earlier switching cycle that does not correspond to substantially the period of the earlier switching cycle divided by the number of converter stages.

Abstract: This invention provides for a transaction card for use at a terminal and for initiating an internet transaction with a SSL protected server, wherein the card comprises a smartcard including an application arranged for extending an SSL connection from the said protected server into the smartcard and, further, the invention can provide for a related terminal, server and related transaction initiation and establishment methods, for extending the said SSL connection as noted above.

Abstract: Disclosed is an intermediate frequency processing device for processing both analogue and digital television intermediate frequency signals including vision and sound intermediate frequency signal components, comprising an intermediate frequency signal input for receiving digital or analogue intermediate frequency signals, a processing section, coupled to said intermediate frequency signal input means, for processing intermediate frequency signals, and an output for outputting signals processed in said processing section. The processing section comprises a first band pass filter (1,2,3) connected to said intermediate frequency signal input, and at least two parallel processing portions (4,6a,7,19-22,30-40,42-45;5,6b,8,18,23-29,46) coupled in parallel to said band pass filter (1,2,3), wherein each of said processing portions includes an inphase quadrature processing means (18,23;19,22).

Abstract: Various exemplary embodiments relate to a method performed by an RFID tag, the method including: receiving a request for a EPC serial number; determining whether the EPC serial number has a preset value; when the EPC serial number has the preset value, mapping a transponder ID to the EPC serial number; and providing the EPC serial number in response to the RFID read request.

Abstract: A governing circuit for a magneto-transistor is disclosed. The magneto-transistor comprising a first and second collector. At least one emitter and at least one base. The governing circuit is configured to measure a first calibration current at the first collector of the magneto-transistor and a second calibration current at the second collector of the magneto-transistor, while a calibration base-emitter voltage is applied to the magneto-transistor. The magneto-transistor is also configured to measure a first measurement current at the first collector of the magneto-transistor and a second measurement current at the second collector of the magneto-transistor, while a measurement base-emitter voltage is applied to the magneto-transistor, wherein the measurement base-emitter voltage is different form the calibration base-emitter voltage and determine an output signal indicative of an applied magnetic field using the measured first and second measurement current and first and second calibration currents.