Abstract: A switched mode power converter is disclosed, together with a method for operating the same. The power converter is adapted to be operable in the boundary conduction mode, and operation is interruptible in the absence of any load requirement.

Abstract: A chip card (1) comprises a chip card controller (3), access to at least one power source (7, 8, 10), a display (6), and a display driver (5) operatively coupled to the chip card controller (3), to the display (6), and to the at least one power source (7, 8, 10). The display driver (5) is configured to drive the display (6) and the display driver (5) comprises, as an integral part, a power management functionality (11) configured to manage power that comes from the at least one power source (7, 8, 10) for at least the display driver (5).

Abstract: A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

Abstract: Orthogonal frequency division multiplexing (OFDM) has become a popular transmission method for high speed wireless radio transmission, due to its potential for low complexity of transmitters and receivers. A method and apparatus are contemplated for cancelling additive sinusoidal disturbances of a known frequency in OFDM receivers which arise e.g. from clock signals that are present for frequency reference, mixer control, and A/D converter control, as well as harmonics and mixing products of those periodic signals, coupling into some point in the receiver chain and appearing as rotating complex exponentials superimposed to complex baseband receive signals. According to the inventive method and apparatus an estimation of an amplitude and phase of a disturbing superimposed tone with a known frequency is obtained and the amplitude and phase estimation is used to cancel the spurious tone preventing a degradation of receiver sensitivity while achieving low implementation complexity.

Abstract: An electronic device is provided which comprises a DC-DC converter. The DC-DC converter comprises at least one solid-state rechargeable battery (B1, B2) for storing energy for the DC-DC conversion and an output capacitor (C2).

Abstract: A container (100) is disclosed comprising a compartment (110); a controller (120) for controlling access to the compartment (110); a near-field communication device (130) for providing the controller (120) with identification information, said controller (120) being responsive to said identification information, wherein the near-field communication device (130) comprises a plurality of antennae (132), each of said antennae being accessible in a different surface area of the container (100). The container (100) may be used in games using near-field communication (NFC) technology, such as a NFC-based version of pass the parcel. An electronic game system (300) comprising such a container and a game controller (200) for use in such an electronic game system (100) are also disclosed.

Abstract: A method of streaming data from a server (S) at a server data rate (Cs) via a network to at least one terminal at a terminal reception data rate (Crec) is provided. A streaming section from the server (S) is requested by the terminal (T). Streaming data is forwarded from the server (S) to the network (N) at a server data rate (Cs) and from the network (N) to the terminal (T) at a reception data rate (Crec). Data received from the network (N) is buffered in the terminal buffer (AL) for at least a first period. The rendering of the buffered data is initiated after the first period at a first rendering rate (Cren), which is lower than the server data rate (Cs) or the reception data rate (Crec). The first rendering data rate (Cren) is adapted according to the filling of the terminal buffer (AL) with received streaming data until the rendering data rate (Cren) corresponds to the server data rate (Cs).

Abstract: A magnetic sensor arrangement for determining information indicative of characteristics of a mechanical component has a first magnetic sensor to sense a signal associated with a periodic changing magnetic field generated by relative movement of the mechanical component and the magnetic sensor arrangement, a second magnetic sensor to sense that signal, wherein the first sensor is arranged a fixed distance from the second sensor, and a determination unit coupled to the first and second sensors to receive output signals of the first and second sensors. The output signal of the first sensor is phase-shifted to the output signal of the second sensor, to compare the output signals for determining the absolute phase of the signal associated with the periodic changing magnetic field, and to determine information indicative of characteristics of the mechanical component based on the determined absolute phase of the signal associated with the periodic changing magnetic field.

Abstract: The invention relates to an electronic component with Sn rich deposit layer on the part for electric connection, wherein the Sn rich deposit layer is a fine grained Sn rich deposit layer composed of grains with smaller size in the direction perpendicular to the deposit surface than in the direction parallel to the deposit surface. It also relates to a process for plating an electronic component, so as to form a Sn rich deposit layer on the part for electric connection, comprising the steps of: adjusting the composition of tin plating solution in which starter additive and brighter additive are included; moving the electronic component through the tin plating solution, so as to form a fine grained Sn rich deposit layer on the part for electric connection. As compared with the prior art, the invention can validly inhibit the whisker growth with low cost and reliable property.

Abstract: An apparatus for storing digital media utilizes an electrically conductive element, which is for reading stored digital media, and multiple electrically conductive resonant circuits as an antenna for radio frequency communications. Each of the resonant circuits is electrically isolated from the other resonant circuits and the electrically conductive element is electrically isolated from each of the resonant circuits. As a result, the apparatus for storing digital media has a relatively wide operating frequency range and a relatively long communications range, which allows worldwide usage in various applications. For example, an optically readable compact disk (CD) utilizes a metal layer configured as a reflective surface for reading stored digital media in the CD, an electrically conductive component that is not in contact with a radio frequency identification (RFID) integrated circuit (IC), and an electrically conductive component that is in contact with the RFID IC, as an antenna for the RFID IC.

Abstract: An LC oscillator is provided that achieves improved phase noise performance. A variable frequency oscillator includes a variable supply source, an oscillator tank circuit, a variable capacitance circuit comprising MOS switches, and an oscillator tank voltage common mode adjustment circuit. When the capacitance of the variable capacitance circuit is varied to vary an output frequency of the variable frequency oscillator, the common mode voltage is adjusted to reduce transitions of the MOS switches between an inversion state and a depletion state during excursions of an output signal through one cycle of oscillation.

Abstract: Tasks are executed in a multiprocessing system with a master processor core (10) and a plurality of slave processor cores (12). The master processor core (10), executes a program that defines a matrix of tasks at respective positions in the matrix and a task dependency pattern applicable to a plurality of the tasks and defined relative to the positions. Each dependency pattern defines relative dependencies for a plurality of positions in the matrix, rather than using individual dependencies for individual positions. In response to the program the master processor core (10) dynamically stores definitions of current task dependency patterns in a dependency pattern memory. A hardware task scheduler computes the positions of the tasks that are ready for execution at run time from information from information about positions for which tasks have been completed and the task dependency pattern applied relative to those tasks.

Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: Consistent with an example embodiment, there is a method of controlling a synchronous rectifier having an input signal having oscillations therein and a switch which is switchable between an open state and a closed state. The method comprises filtering the input signal to produce a filtered signal, comparing the filtered signal with a reference value, and opening the switch in response to the comparison, in which the filtering is active filtering. The active filtering may be based on determination of the peaks (positive and/or negative) of the signal, either directly, including a quarter period offset, or including decay—or a combination of the above; alternatively, the active filtering may be based on the a smoothing functions such as a switched low-pass filter or a short time integrator.

Abstract: Active load modulation antennas for contactless systems typically require the presence of a battery power source in the transponder device. The transponder typically cannot be powered by the reader device alone and also transmit an active load modulation signal. Embodiments in accordance with the invention are disclosed that allow transponder devices to transmit an active load modulation signal when powered only by the reader in the contactless system.

Abstract: A voltage regulator circuit and a method for operating the voltage regulator circuit are described. In one embodiment, a voltage regulator circuit includes an input terminal to receive an input signal from a power interface, an output terminal to output an output signal using the input signal, an output voltage monitor circuit configured to compare the voltage of the output signal with a predetermined voltage threshold, and a current limit circuit configured to limit current flowing on a path from the input terminal to the output terminal to a transient current limit level. The transient current limit level is lower than a predefined current limit threshold of the power interface. Other embodiments are also described.

Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the passivation layer and electrically coupled to the circuit. A wire is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Abstract: Embodiments of a method for preparing a leadframe for integrated circuit (IC) die packaging in a molded package with an exposed die pad are disclosed. In one embodiment, a method involves producing a leadframe with a die pad, wherein the die pad has a top surface, a bottom surface, and a perimeter edge. The die pad is then planarized to flatten burrs that may exist at the perimeter edge of the die pad, wherein planarizing the die pad comprises embedding tool markings in the die pad at the perimeter edge of the die pad, the tool markings including a series of peaks and valleys that run parallel to the perimeter edge at all locations around the perimeter edge. Embodiments of a leadframe for IC die packaging in a molded package are also disclosed.

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.