Abstract: A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 interfacial layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.

Abstract: A method for managing expired or consumed applications (app1, app2 . . . appx) that have been provided by a Service Provider (SP) and are stored in a memory element (SE) of a mobile communication device (MOB), e.g. a NFC mobile phone, comprises storing a representation (RP) of expired or consumed applications (app1, app2 . . . appx) in or on a storage medium that is separate from the memory element (SE).

Abstract: A method of operating a micro-electromechanical system, comprising a resonator; an actuation electrode; and a first detection electrode, to filter and mix a plurality of signals. The method comprises applying a first alternating voltage signal to the actuation electrode, wherein an actuation force is generated having a frequency bandwidth that is greater than and includes a resonant bandwidth of a mechanical frequency response of the resonator, and wherein a displacement of the resonator is produced which is filtered by the mechanical frequency response and varies a value of an electrical characteristic of the first detection electrode. The method also comprises applying a second alternating voltage signal to the first detection electrode, wherein the second voltage signal is mixed with the varying value to produce a first alternating current signal. The first alternating current signal is detected at the first detection electrode.

Abstract: In one embodiment, a regulator circuit is provided. The regulator circuit includes a control circuit configured and arranged to adjust an oscillation frequency of a variable frequency oscillator in response to a feedback signal indicating the regulated output voltage. A charge pump is coupled to an output of the variable frequency oscillator and is configured to charge one or more energy storage elements in response to the output of the variable frequency oscillator. The regulator circuit includes a plurality of output stages, each having an input driven by the output of the charge pump and being configured to drive the regulated output voltage. Each output stage is selectably enabled or disabled in response to respective enable signal provided to the output regulator by an enable control circuit.

Abstract: In a communication partner device (1) intended for the contactless transmission of digital data to be transmitted having a transmission circuit (2), the transmission circuit (2) comprises a modulation circuit (17) for the amplitude modulation of a carrier signal (CS), which modulation circuit (17) comprises a circuit stage (20, 20?) for producing a plurality of different resistance values (RW 1, RW 1?) that act on a signal output (TX1, TX2), which resistance values (RW1, RW1?) can be transformed, by means of a signal processing circuit (3) arranged to transform resistance values that belongs to the communication partner device (1), into transformed resistance values (RW2, RW2?), which transformed resistance values (RW2, RW2?) are responsible for damping a transmission coil (7) of the communication partner device (1) when modulated low-level carrier signal sections are generated in a modulated carrier signal.

Abstract: The present invention relates to a dimmer control circuit (100) capable to detect whether a phase-cut dimmer is connected using an average signal (VDCI) derived from the mains voltage. The average signal (VDCI) or a signal (VDCI_ls) derived from (VDCI), ranging from a minimum value to a maximum value, is compared to a dimming threshold (Vdim_th) through a phase-cut detecting unit (20). The comparison result is used to control the state diagram of a dimmer control logic (40) by selecting the step dimming mode (STD) or the phase-cut dimming mode (PCD). The output (OUT) of a switching unit (30) is determined by the state diagram of the dimmer control logic (40) in such a manner that the phase-cut dimming mode (PCD) is prioritized above the step-dimming mode (STD) and the maximum level of the STD states is depending on the mains voltage and application adjustable.

Abstract: In one embodiment, a circuit is provided. The circuit includes a low-ohmic circuit and a a power supply node configured and arranged for providing a supply voltage across the low-ohmic circuit to a load from which current can be drawn. The circuit also includes a current reference circuit, configured and arranged for setting a current reference level that is based on a portion of the current from the power supply node, and a current-sensing circuit. The current-sensing circuit senses and is responsive to current passing through the low-ohmic circuit. The current-sensing circuit operates in a normal mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is less than the current threshold level, and in an over-current mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is greater than the current threshold level.

Abstract: A mobile communication device (1, 10) comprises shielding components that provide electromagnetic shielding or attenuation between a first area (A) and a second area (B, B1, B2) within and/or external of the communication device (1, 10). In said first area (A) an antenna (4) and at least one ferrite (6) are arranged, which ferrite (6) is provided to interact with said antenna (4) and to guide a magnetic flux between said first area (A) and said second area (B, B1, B2).

Abstract: An immobilizer device is configured for communicating with a base station. The immobilizer device includes an antenna circuit including three orthogonally-oriented antennas configured to receive a signal from a field generated by a base station. A power circuit is configured to draw power via the field on each of the antennas, and a communications circuit is configured to communicate with the base station via any of the antennas. The strength of the signals received via the antennas is evaluated and used to select one of the antennas for use in data communications and, if appropriate, as a power supply.

Abstract: A processing unit for processing a multi-channel audio signal has a delay element (40) for delaying an FM sum signal (sum) and a converter arrangement (T) for converting an FM difference signal (duff) and a noise signal (diffnoise) to the frequency domain. Frequency-based noise suppression is used to derive a de-noised frequency-domain difference signal using a gain function which is limited to a maximal and a minimal value. This is then converted to the time domain, and the first and second audio signals are calculated from a delayed sum signal (sum2) and the de-noised time domain difference signal (diff2).

Abstract: A method (and system) of processing image data in which a depth map is processed to derive a modified depth map by analysing luminance and/or chrominance information in respect of the set of pixels of the image data. The depth map is modified using a function which correlates depth with pixel height in the pixellated image and which has a different correlation between depth and pixel height for different luminance and/or chrominance values.

Abstract: In an example embodiment, an integrated circuit (IC) comprises a substrate separating one of a source and drain from a semiconductor region. The IC comprises a vertical transistor including the source or drain. A gate electrode is formed in a trench extending into the semiconductor region; the gate electrode is electrically insulated from the semiconductor region by a dielectric lining in the trench and the other of said source or drain in the semiconducting region. An insulating trench terminates the vertical transistor; a vertical capacitor region (V-Cap) is adjacent to the vertical transistor; a first capacitor plate of the V-Cap comprises the source or drain separated from the semiconductor region by the substrate; the V-Cap further comprises at least one trench extending into the semiconductor region; the at least one trench comprises an electrically insulating liner material insulating a conductive material defining a second capacitor plate separated from the first capacitor plate.

Abstract: A semiconductor package, comprises an encapsulant which contains a semiconductor substrate, the package lower side being mountable on a surface. The semiconductor substrate backside is in close proximity of the semiconductor package lower side for improved thermal conductivity to the surface. The active side of the semiconductor substrate, facing the upper side of the semiconductor package, has a plurality of die contacts. A plurality of electrically conductive interconnects are connected to the die contacts and extend to the lower side of the semiconductor package for connecting the die contacts to the surface.

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance while being efficient in utilization of semiconductor real estate.

Abstract: An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

Abstract: Consistent with an example embodiment there is a method for regulating a LED current (ILED) flowing through a LED circuit arrangement at a mean LED current level. The method includes establishing an oscillating converter current (IL), establishing a first and a second current control indicator representative of a flow of a converter current (IL); regulating a peak and valley current level of the converter current in dependence on the first current control indicator; controlling a converter current period (T) of an oscillation of the converter current in dependence on the second current control indicator to be within a period control range (Tref) and feeding at least part of the converter current to the LED circuit arrangement.

Abstract: A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a boron-doped further silicon layer over the resultant structure; forming dielectric spacers on the trench sidewalls; filling the trench with emitter material; exposing polysilicon regions outside the trench side walls by selectively removing the sacrificial layer; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing

Abstract: A combination amplifier, in particular a Doherty amplifier allowing dynamic biasing, is provided, the combination amplifier comprising a first amplifier (3,3a,3b) having a first input terminal (11,11a,11b) and a first output terminal (25,25a,25b); a second amplifier (5,5a,5b) having a second input terminal (27,27a,27b) and a second output terminal (29,29a,29b); a first impedance inverter (Li, 43b) connected between the first input terminal and the second input terminal; and an envelope detector (33,33a,33b) comprising a detector output terminal and a detector input terminal which is connected to the first output terminal.

Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (14). A sacrificial layer (20) is provided over the device element and a package cover layer (22) is provided over the sacrificial layer. The sacrificial layer is removed using at least one opening (22) in the cover layer and the at least one opening (24) is sealed by an anneal process.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.