Patents Assigned to NXP
  • Patent number: 8542118
    Abstract: A presence detection system for detecting objects which move through an entrance of a space. The system is based on the idea to create a signature of a moving object which can be used to determine whether the object is a human being.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Ghiath Al-Kadi, Aly Aamer Syed, Ewout Brandsma
  • Patent number: 8542017
    Abstract: A system and method for measuring the shape of an object using a magnetic induction radio sensor involves at least partially enclosing the object with a magnetic loop antenna of the magnetic induction radio sensor, where the inductance of the magnetic loop antenna depends on the shape of the object, and providing a particular capacitance at an antenna matching circuit coupled to the magnetic loop antenna in response to the inductance of the magnetic loop antenna such that the magnetic loop antenna and the antenna matching circuit form a resonant circuit and the resonant circuit has a fixed resonant frequency, where the particular capacitance is used to measure the shape of the object.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventor: Steven Aerts
  • Patent number: 8542827
    Abstract: An apparatus and method for generating a shared secret between at least two wireless portable electronic devices. A shared secret is generated by holding together the at least two devices and shaking them. An acceleration of the at least two devices is measured at least during a time window beginning at a time corresponding to when a magnitude of the acceleration exceeds a predetermined threshold. The acceleration is sampled, resulting in a plurality of vectors, such that a first vector is an initial sample of the acceleration during the time window. In some embodiments, the acceleration is measured in three dimensions. Dot products are calculated between the first vector and each of a plurality of subsequent vectors, resulting in an array of scalars. At least a portion of this array is used to generate the shared secret between the at least two devices.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventor: Charles Razzell
  • Patent number: 8541812
    Abstract: A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Philippe Meunier-Beillard, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Guillaume Boccardi
  • Patent number: 8542052
    Abstract: An electrical circuit for emulating a capacitance, comprises a physical capacitor which is charged by charge flow from the input of the electrical circuit. An amplifier amplifies the voltage at the input of the electrical circuit such that the physical capacitor is charged with a larger change in voltage than the change in voltage at the input. This implements an effective multiplication of capacitance. A reset system resets the physical capacitor without drawing charge from the input of the electrical circuit. This extends the voltages which can be provided to the input.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventor: Hans Halberstadt
  • Patent number: 8544008
    Abstract: A data processing system is provided with at least one processing unit (1) for an interleaved processing of multiple tasks (T1-T3), and a cache (5) associated to the at least one processing unit (1) for caching data for the multiple tasks (T1-T3) to be processed by the at least one processing unit (1). The cache (5) is divided into a plurality of cache lines (6). Each of the cache lines (6) is associated to one of the multiple tasks (T1-T3). Furthermore, a task scheduler (10) is provided for scheduling the multiple tasks (T1-T3) to be processed in an interleaved manner by the at least one processing unit (1). A cache controller (20) is provided for selecting those cache lines (6) in the cache (5), which are to be evicted from the cache (5). This selection is performed based on the task scheduling of the task scheduler (10).
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Sainath Karlapalem, Bijo Thomas, Nagaraju Bussa
  • Patent number: 8541992
    Abstract: A DC voltage converter, comprising: a multi-ratio capacitive converter; a linear voltage regulator in series with the multi-ratio capacitive converter; and a controller; the controller arranged to control the ratio of the multi-ratio capacitive converter dependent upon the voltage difference across the linear voltage regulator.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Hendrik Johannes Bergveld, Franciscus Adrianus Cornelis Maria Schoofs
  • Patent number: 8541865
    Abstract: The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Jean-Marc Yannou, Johannes Van Zwol, Emmanuel Savin
  • Patent number: 8541267
    Abstract: The present invention relates to a method for fabricating a FinFET on a substrate. The method comprises providing a substrate with an active semiconductor layer on an insulator layer, and concurrently fabricating trench isolation regions in the active semiconductor layer for electrically isolating different active regions in the active semiconductor layer from each other, and trench gate-isolation regions in the active semiconductor layer for electrically isolating at least one gate region of the FinFET in the active semiconductor layer from a fin-shaped channel region of the FinFET in the active semiconductor layer.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Jan Sonsky, Anco Heringa
  • Patent number: 8541786
    Abstract: The invention relates to semiconductor devices and methods of manufacturing. In certain embodiments, a semiconductor device can include: a) a contact pad with pre-shaped sidewalls; b) a semiconductor chip having a terminal that is electrically connected to the contact pad, and c) a protective compound covering the semiconductor chip and at least part of the sidewalls. The sidewall can be rough or the sidewall can be tapered to facilitate locking of the contact pad into the compound.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Rene Wilhelmus Johannes Maria van den Boomen, Jan van Kempen
  • Patent number: 8543746
    Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventor: Jens Roever
  • Publication number: 20130240999
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 19, 2013
    Applicants: NXP B.V., STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alexandre Mondot, Markus Mueller, Thomas Kormann
  • Patent number: 8536945
    Abstract: A differential output stage configured for receiving differential input signal comprising first and second signals, comprising a first output for providing a first output signal, and a second output providing a second output signal, the first and second output signals together forming a differential output signal, a first voltage buffer and first controlled current source each connected to the first output, the first voltage buffer being driven by a signal in-phase with the first input signal, the first controlled current source being driven by a signal in-phase with the second input signal, and a second voltage buffer and second controlled current source each connected to the second output, the second voltage buffer being driven by a signal in-phase with the second input signal, the second controlled current source being driven a signal in-phase with by the first input signal.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: September 17, 2013
    Assignee: NXP B.V.
    Inventor: Gian Hoogzaad
  • Patent number: 8537905
    Abstract: The present invention relates to adjustment of interconnect power levels in high-speed differential serial links. In an example embodiment, a digital signal received at a digital input port is converted in a driver into a corresponding differential signal and provided to output ports connected to a differential transmission line for provision to a receiver. For adjusting the interconnect power levels between the driver and the receiver a voltage regulator is interposed between a voltage source and the driver. The voltage regulator provides regulated supply voltage to the driver. In operation, the voltage regulator receives from control circuitry a control signal indicative of a predetermined regulated voltage for provision to the driver for a pre-selected type of data transmission. In dependence upon the received control signal the voltage regulator selects the corresponding reference voltage and provides it to the driver.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: September 17, 2013
    Assignee: NXP B.V.
    Inventor: Elie Khoury
  • Patent number: 8534914
    Abstract: A method of estimating the junction temperature of a light emitting diode comprises driving a forward bias current through the diode, the current comprising a square wave which toggles between high and low current values (Ihigh, llow), the high current value (lhigh) comprising an LED operation current, and the low current value (ILOW) comprising a non-zero measurement current. The forward bias voltage drop (Vf) is sampled and the forward bias voltage drop (Vflow) is determined at the measurement current (ILOW)—The temperature is derived from the determined forward bias voltage drop.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: September 17, 2013
    Assignee: NXP B.V.
    Inventors: Viet Nguyen Hoang, Radu Surdeanu, Pascal Bancken, Benoit Bataillou, David Van Steenwinckel
  • Patent number: 8539292
    Abstract: An integrated circuit comprises a scan chain with parallel inputs and outputs coupled to a functional circuit. A scan chain modifying circuit is provided coupled to the scan chain. When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain or operation of functional circuits.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: September 17, 2013
    Assignee: NXP B.V.
    Inventors: André K. Nieuwland, Sandeepkumar Goel, Erik J. Marinissen, Hubertus G. H. Vermeulen, Hendrikus P. E. Vranken
  • Patent number: 8538481
    Abstract: A processing device having a housing includes first communication device for receiving and/or transmitting an information signal and processor for processing the information signal received and/or to be transmitted, as well as second communication device for the contactless retrieval of control information stored in a data carrier which is detachably connected to the of the processing device, which processing of the information signal by the processing device can be influenced with the aid of the retrieved control information.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 17, 2013
    Assignee: NXP B.V.
    Inventors: Reinhard Meindl, Stefan Posch
  • Patent number: 8536926
    Abstract: A Gilbert mixer (200) comprising four switching transistors (Q3, Q4, Q5, Q6), two intermediate frequency transistors (Q1, Q2), and one or more DC decoupling components (202). The one or more DC decoupling components (202) are coupled between the switching transistors (Q3, Q4, Q5, Q6) and the intermediate frequency transistors (Q1, Q2) in order to DC decouple the switching transistors (Q3, Q4, Q5, Q6) from the intermediate frequency transistors (Q1, Q2).
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 17, 2013
    Assignee: NXP B.V.
    Inventors: Ying Chen, Marcel Geurts
  • Publication number: 20130233086
    Abstract: A pressure sensor measures pressure by measuring the deflection of a MEMS membrane using a capacitive read-out method. There are two ways to implement the invention. One involves the use of an integrated Pirani sensor and the other involves the use of an integrated resonator, to function as a reference pressure sensor, for measuring an internal cavity pressure.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 12, 2013
    Applicant: NXP B. V.
    Inventors: Willem Frederik Adrianus Besling, Martijn Goossens, Jozef Thomas Martinus van Beek, Peter Gerard Steenken, Olaf Wunnicke
  • Publication number: 20130238573
    Abstract: Various exemplary embodiments relate to a method of compressing location data. The method may include: receiving original location data; selecting a contextual profile based at least in part on the original location data; selecting a compression method based on the contextual profile; and converting the original location data to a compressed format based on the compression method. Various exemplary embodiments relate to a system for compressing location data. The system may include: a location receiver configured to generate original location data based at least on signals from global navigation satellite system (GNSS) satellites; a location engine configured to select a contextual profile based at least in part on the original location data; and a contextual compression filter configured to generate compressed location data in a compressed format based on the selected contextual profile.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 12, 2013
    Applicant: NXP B.V.
    Inventor: Pierre LE PIFRE