Abstract: Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.

Abstract: Level-shifting devices and methods allow signals to be passed between input/output (I/O) ports. One such device comprises a first output driver that drives a first I/O port in response to a first control signal. A second output driver drives a second I/O port in response to a second control signal. A first comparator circuit, responsive to a first reference voltage and a voltage at the first I/O port, generates the second control signal. A limiter circuit limits driving of the second I/O port, by the second driver, to a limiting voltage that responsive to a the second I/O port over a first range of signaling voltages, and constrained to a set value over a second range. A voltage reference generating circuit generates a second reference voltage. A second comparator circuit generates the first control signal in response to the second reference voltage and the second I/O port.

Abstract: The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacitance hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.

Abstract: A transmitter/receiver circuit comprises a wireless transmission/reception circuit having a first inductor for generating/detecting a magnetic induction field onto which an output of a radio frequency circuit is modulated and a second inductor in series with the first inductor for generating/detecting an electric induction field onto which the output of the radio frequency circuit is modulated. The second inductor comprises an electrically conductive track which at least partially surrounds a grounded electrically conductive core. The invention thus provides the transmitter and receiver for a communication system using near fields, and in which the input/output of the radio frequency circuitry can be balanced. The first coil produces the main magnetic induction field and the second coil is activated as an antenna producing an electric induction field. By this method, the operating range is increased and the relative positioning between both communication ends is less sensitive.

Abstract: Systems and methods according to the present invention provide serial communication devices which are pin-configurable at power on to operate as either a root (20) or endpoint (22) device. In conjunction with, for example, PCI Express specified I/O data buses (24), such devices provide for efficient transfer of serial data between systems and devices.

Abstract: A peripheral device and a method for programming the read/writeable memory of the RFID circuitry by communications between either RF antenna or bus communications port controller interface or both. In the peripheral device, an EEPROM, bus communications controller interface, NFC interface, antenna, and logic controller operate to receive and transmit configuration and calibration data between a wireless personal area network circuit and an external wireless personal area network enabled device. The dual interfaced EEPROM is operable to share or partition its EEPROM between an NFC interface and a bus communications controller.

Abstract: A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer.

Abstract: Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a schedule allocates the data and schedule to a plurality of computational units. The scheduler also modifies voltage and frequency settings of the processing architecture to optimize power consumption and throughput of the system. The computational units include control units and execute units. The control units receive and decode the instructions and send the decoded instructions to execute units. The execute units then execute the instructions according to relevant software.

Abstract: A transmitter (200) comprises a first Chireix compensation circuit (230, 232, 238, 240) and a second Chireix compensation circuit (234, 236, 238, 240), wherein each Chireix compensation circuit has two inputs and two outputs. Two constant envelope input signals (22, 224) to be amplified are guided by a switch (226) to either the first or second Chireix amplifier unit. The selection as such depends on the phase (212) of the input signals to be amplified. The outputs of the two Chireix compensation circuits are cross-coupled to an inductive load (242). A Chireix inductor (238) and a Chireix capacitor (240), each having one terminal grounded, are also connected to the inductive load (242). By switching the signals to be amplified in response to their phase, optimum matching is ensured.

Abstract: A data processing system comprises multiple data processing nodes that communicate with one another using the FlexRay protocol. Each respective node works according to a respective schedule based on a repetitive sequence of cycles, each cycle having a sequence of time slots. Each node executes instructions, one per time slot, if any. The instructions are stored in a memory. Each instruction is identified by the relevant cycle number and time slot number in the relevant cycle. Accordingly, the combination of cycle number and slot number identify a memory address. Typical instructions appear more than once in the repetitive sequence of cycles for a node. This temporal pattern of occurrences of the same instruction at a node is used to modify the generation of the memory addresses, so that the same memory address is generated each time the instruction is needed. This makes efficient use of storage space.

Abstract: According to certain embodiments, a non-volatile memory device on a semiconductor substrate having a semiconductor surface layer comprises a channel region that extends in a first direction between the source and drain regions. The gate is disposed near the channel region and the memory element is disposed in between the channel region and the gate. The channel region is disposed within a beam-shaped semiconductor layer, with the beam-shaped semiconductor layer extending in the first direction between the source and drain regions and having lateral surfaces extending parallel to the first direction. The memory element comprises a charge-trapping stack so as to embed therein the beam-shaped semiconductor layer in a U-shaped form.

Abstract: A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage application unit is arranged to write data by switching each cell between a first resistance state and a second, lower, resistance state. The voltage application unit is arranged to switch a cell to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by 0.5 volts or less. The voltage application unit is arranged to switch a cell to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by 0.5 volts or less.

Abstract: A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a boron-doped further silicon layer over the resultant structure; forming dielectric spacers on the trench sidewalls; filling the trench with emitter material; exposing polysilicon regions outside the trench side walls by selectively removing the sacrificial layer; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing

Abstract: An RF switch for an RF splitter is disclosed, in which the bias voltage for the RF switching elements can be supplied, by using an RF to DC translator, from the RF signal on the input side to the switch. By using a native NMOS switch, routing of the RF signal is thus enabled without the necessity for an external power supply.

Abstract: The time slot index for wireless signals is synchronized using an approach that facilitates rapid synchronization acquisition and tracking synchronization recovery. According to an example embodiment, a synchronization circuit (e.g., 300) uses data in symbols of a particular signal frame (e.g., 120) to set a time slot index synchronization characteristic for an acquired wireless signal, and further to track time slot index synchronization during processing of the signal.

Abstract: An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second header followed by at least one boundary scan test input bit. The bit stream and the clock are extracted and occurrences of the first header and second header are detected. Based on the detected occurrences the boundary scan mode bits and boundary scan input bits are identified and distributed to the electronic circuit, along with the extracted clock, and boundary scan test is performed.

Abstract: A level shifter for a set of at least three phase-shifted signals is disclosed. The level shifter comprises an odd plural number of inverters arranged in a ring. A supply terminal of each inverter is coupled to a supply rail via a respective switching device, which is controlled by the phase-shifted signals.

Abstract: A track and hold circuit has a main transistor for which the gate voltage is provided by a buffer circuit which is supplied with a different voltage supply than the circuit of the main transistor. This avoids the need for a bootstrap circuit.

Abstract: A variety of near-field devices, methods and systems are implemented in various fashions. One implementation is directed to a mobile station (102) with an over-the-air (OTA) transceiver (104) for communication with a trusted service manager. The mobile station also has a near-field communications transceiver (112) for communication with a terminal reader using file-identifiers of a first size. A memory (106) is used for storing files arranged according to two different sets of files, the first set of files identified by file-identifiers of a first size and the second set of files identified by file-identifiers of a second size that is a different size from the first size. A processor (108) provides access by the OTA transceiver (104) to the stored files. Access by the near-field communications transceiver (112) is provided to the stored files by running either a Java-based emulator for accessing the first set of files or Java APIs to access the second set of files.

Abstract: Consistent with an example embodiment, there is method and a controller for controlling burst mode operation of a switched mode power supply (SMPS). It also relates to switched mode power supplies comprising such a controller. One way to increase the efficiency of a switched mode power supply is to operate it at a power level close to the optimum efficiency point for a brief period, followed by a period where the power supply is not switching during which no energy is wasted. This type of operation is known as “burst mode” and results in high efficiency at low power levels.