Abstract: Semiconductor dice (100, 200) of integrated circuit chips are provided with solder bump pads (130, 230) distributed over active areas of the dice to supply the I/O interconnects without including peripheral wire bond pads. The dice are further provided with protective ESD structures (140p/140i, 240p/240i) arranged in a network that includes ESD structures that extend into the interior areas of the dice. This allows the ESD structures to be placed proximate to respective power and ground connections, and positioned to reduce an average interconnect length between interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.

Abstract: A switched mode power converter controller outputs a switch control signal for a switch, receives sensed voltage and primary current input signals, and includes a constant current mode controller to process voltage input signals and generate output control signals for controlling converter peak current and/or switching frequency operational; a constant voltage mode controller processes the voltage input signal and generates output control signals for converter peak current and/or switching frequency operational parameters; a primary peak current adjuster processes primary current input and output control signals from the current and voltage mode controllers to configure the switch control signal to turn off the switch; a switching frequency adjuster processes output control signals from the current and voltage controllers to configure the switch control signal to turn on the switch.

Abstract: A device and method for encoding bits to symbols for a communication system are described. In one embodiment, a method for encoding bits to symbols for a communication system includes receiving a set of N-bit data to be transmitted, where N is an integer, generating side scrambling values using a polynomial, scrambling the set of N-bit data using the side scrambling values to produce scrambled data, mapping the scrambled data to a particular set of M symbols from a plurality of sets of M symbols, where M is an integer and M is smaller than N, and outputting the particular set of M symbols for transmission over a transmission medium. Other embodiments are also described.

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: The present invention relates to a voltage control circuit, semiconductor memory device, and method of controlling a voltage in a phase-change memory, wherein the voltage control circuit generates a controlled voltage which can be above the logic supply voltage. This voltage can limit the bit line voltage in a phase-change memory to allow the use of smaller transistors in the memory cells and in the program current part of the circuit. This results in smaller memory cells and modules.

Abstract: A planar inductive unit having at least one operating frequency is provided. The inductive unit comprises at least one inductor winding (120) having a first width (121) and a centre (122) and being arranged in a first plane. The inductive unit furthermore comprises at least one ground path (200) having a first section (205) extending in the first plane and at least a second section (210) with a second width (211) extending in at least a second plane.

Abstract: The invention relates to a programmable filter for a radiofrequency receiver, embodiments disclosed including a filter (600) comprising an input (601) for receiving a radiofrequency signal, an output (602) for providing a filtered version of the input radiofrequency signal and a plurality of filter paths (603a-c) connected in parallel between the input (601) and output (602), each filter path comprising a buffer (604a-c) connected between the input (601) and one or more polyphase filters (605a-f), wherein each of the plurality of filter paths (603a-c) is configured to be individually selectable by providing an enable signal to a corresponding one of the buffers (604a-c).

Abstract: The invention deals with the control of a resonant LLC converter by setting up criteria for state parameters of the resonant converter, so that the converter may be operated in a near capacitive mode. The current flowing in the resonant tank and optionally the voltage at the a predetermined point in the resonant tank are monitored, and wherein a switch (a high side switch or a low side switch) is turned off when a first criterion is fulfilled together with a second criterion or optionally a third criterion, the first criterion ensuring a minimum time has lapsed after the switch is turned on, the second criterion being that the absolute value of the current is reaching a predetermined current level, the third criterion being that the voltage at the predetermined point reaches a predetermined voltage level.

Abstract: A system and method for providing fault detection capability is provided which comprises a first node (2). The first node (2) comprises a first processing subsystem (5) generating data (14) to be transmitted. The first node (2) has a fault supervisor unit (13) adapted to gather and process fault indications arising in the first node (2). The first processing subsystem (5) and the fault supervisor unit are both integrated in the first node (2). The first node (2) is structured such that, when no fault indications are detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a first key (15) as a validity key, and, when at least one fault indication is detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a second key (16) as the validity key, and the data (14) to be transmitted are encrypted by overlaying the respective validity key (15; 16) on the data.

Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14?), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

Abstract: A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

Abstract: A processor (10) of processes data using a cache circuit (12). The processor (20) is coupled to a functionally detachable device (19) via the cache circuit (12). When a cache line is loaded into cache memory (120), it is tested whether the cache line has an address within a detachable device address range allocated to the detachable device (19). If so, identification of the cache line, or a range of addresses that includes the address of the cache line is stored. When a flush command is received that requires write back cached data to the detachable device, the identification is used to select the cache line for selective write back to the detachable device. Thus less cache data needs to be invalidated when a device is functionally detached from the circuit.

Abstract: An inductive component for a DC/DC converter is made by transferring a copper track (2) from a copper substrate (1) to a first ferrite plate (3). A second ferrite plate (5) is attached by glue to the first ferrite plate so that the track (2) forms an inductor coil sandwiched between the two ferrite plates (3,5). One of the plates has holes (4) in registration with the terminals of the coil, and these holes are filled with solder (5) to provide externally accessible contacts.

Abstract: The application relates to a digital modulator comprising at least one input terminal configured to receive at least one signal, at least one symbol generating unit comprising a first output terminal and at least a second output terminal, wherein the symbol generating unit is configured to generate a first symbol waveform for the first output terminal depending on the received signal, and wherein the symbol generating unit is configured to generate at least a second symbol waveform for the second output terminal depending on the received signal, wherein the first symbol waveform comprises at least one different parameter value compared to the second symbol waveform, at least one third output terminal connectable to at least the first output terminal and/or second output terminal via a switching unit, a controlling unit configured to control the switching unit depending on the received signal such that a modulated output signal is generated.

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).

Abstract: System and method for compensating for changes in an output impedance of a power amplifier uses an impedance compensating circuit with an impedance inverter coupled to the power amplifier. The impedance inverter of the impedance compensating circuit is configured such that an output impedance of the impedance inverter is proportional to the inverse of the output impedance of the power amplifier to compensate for changes in the output impedance of the power amplifier.

Abstract: A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source-synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).

Abstract: In multi-carrier systems, distributed resource allocation of the resources of multiple user equipments (UEs) can result in better frequency diversity gain but can also induce Inter-Carrier Interference (ICI) between UEs. This ICI can become quite serious in a high mobility environment. Based on a novel radio channel model for ICI cancellation in multi-carrier systems and an iterative channel estimation scheme for ICI cancellation in multi-carrier systems, the present invention provides a simplified equalization scheme in the frequency domain to determine and remove ICI of both a targeting UE as well as other UEs.

Abstract: A bond wire circuit includes at least three bond wires arranged to split an input signal into two output signals. In connection with various example embodiments, bond wires are arranged in a generally parallel manner to mitigate magnetic coupling and related issues for splitting an input signal and providing each of split signals to an amplifier. The bond wires are connected by capacitive circuits that facilitate the splitting, and in some applications, additional capacitive (to ground/reference) and load circuits to further facilitate the splitting of the input signals for specific amplifier circuit implementations, and applications to various loads. In some implementations, the input signals are split in equal or arbitrary portions with frequency independent phase differences in a wide frequency band, with isolation between ports of the circuit.

Abstract: A method of manufacturing a Bulk Acoustic Wave device by providing an active layer formed of an electro-mechanical transducer material, providing a first electrode on the active layer, defining a first electrode portion of the device, whereby a remaining portion of the device is defined around the first electrode, providing a stop-layer on the first electrode, depositing a first dielectric layer on the resultant structure, and planarizing the first dielectric layer until the stop-layer on the first electrode is exposed.