Abstract: A method is disclosed of compensating the output of an ADC for non-linearity in the response of the ADC. The method comprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.

Abstract: An integrated circuit comprises a plurality of clock domains (10, 12). Test data is shifted into the integrated circuit through a scan chain (100, 14, 104). In a test mode a connection is interrupted between a functional output of a first clock domain (10) and a functional input of a second clock domain (12). Test data is applied from the scan chain (100, 14, 104) to the functional input and a test response is captured into from the functional output. A delay circuit (24, 28) is used to delay transfer of the test result from the scan cell (21) to the functional input when the test result is captured in the scan cell (21), to ensure that timing differences between the clock domains do not affect the test. Subsequently the test result is shifted through the scan chain.

Abstract: Disclosed is a photosensitive system including a gated photodiode having at least one field plate and a cathode and an output buffer having an input coupled to the gated photodiode for reducing the impedance of the photodiode signal and having an output for providing the reduced impedance signal. The output is electrically connected to the at least one field plate. A device including such a photosensitive system is also disclosed.

Abstract: A power supply circuit and a method for operating the power supply circuit are described. In one embodiment, a power supply circuit includes multiple power elements configured to convert an input voltage to an output voltage, a driver circuit coupled to the power elements and configured to drive the power elements, a regulator controller coupled to the power elements and configured to control the power elements for the conversion of the input voltage to the output voltage, and at least one bypass switch coupled to the power elements. The at least one bypass switch is used to bypass at least one of the power elements. Other embodiments are also described.

Abstract: A controller (210) for a switched mode power supply (100), the switched mode power supply (100) comprising one or more windings (104, 108, 108). The controller (210) comprising a fixed speed timer (236); a threshold setter configured to a set a threshold for the timer (236) in accordance with a peak value of a current (304) through one of the one or more windings (106); a secondary stroke detector (252) configured to start the fixed speed timer (236) upon detection of the start of a secondary stroke of the switched mode power supply; a sampler (232, 234) configured to sample a voltage across one of the one or more windings (108) when a count of the fixed speed timer (236) reaches the threshold.

Abstract: A star network (1) having a star coupler (14) and at least a first and second network branch (112, 122), wherein each network branch (112, 122) comprises at least one network node (110, 120) and a bus driver (11, 12) connected between the star coupler (14) and the at least one network node (110, 120). A first bus driver (11) of the first network branch (112) is adapted to detect a symbol pattern comprising at least two predetermined equal control symbols, which are transmitted from the first network node (110) to the second network node (120), wherein a control symbol is part of a control pattern. The control pattern is used to force at least the second network node (120) to switch into a predetermined state. The first bus driver (11) is disabling the first network branch (112) from the star network (1) based on whether the transmitted symbol pattern is detected. By using the protection mechanism a reliable detection of babbling idiots is provided.

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: A device (100) for managing a plurality of software items, the device (100) comprising an analysis unit (103) adapted for analyzing a functional correlation between the plurality of software items, and a grouping unit (105) adapted for grouping functionally correlated ones of the plurality of software items together in a common memory space.

Abstract: A method for reproducing audio and/or video content on a device is provided. A position of a user is determined. Audio and/or video content to be reproduced on the device is selected based on the position of the user and is reproduced on the device. If the determined position of the user is in a first region (1), at least one first audio and/or video 5 content is selected. If the determined position of the user is in a second area (2), at least one second audio and/or video content is selected. If the determined position of the user is in an overlap region of the first and second area or in a region between the first and second area, a third audio and/or video content is generated based on at least the first and/or second audio and/or video content and the third audio and/or video content is selected to be reproduced.

Abstract: An electrode for an ionization chamber and an ionization chamber including an electrode are provided wherein the electrode comprises a substrate comprising a first material, and a plurality of nanowires extending from the substrate and manufactured by processing the first material of the substrate.

Abstract: Disclosed is a pH sensor comprising a carrier (10) comprising a plurality of conductive tracks and an exposed conductive area (40) defining a reference electrode connected to one of said conductive tracks; a sensing device (30) mounted on the carrier and connected at least one other of said conductive tracks; an encapsulation (20) covering the carrier, said encapsulation comprising a first cavity (22) exposing a surface (32) of the sensing device and a second cavity (24) exposing the exposed conductive area, said second cavity comprising a reference electrode material (42) and an ion reservoir material (44) sharing at least one ion type with said reference electrode material, the reference electrode material being sandwiched between the exposed conductive area and the ion reservoir material. A method of manufacturing such a pH sensor is also disclosed.

Abstract: Central bus guardians (CBGs) and methods for operating a CBG are described. In one embodiment, a method for operating a CBG includes performing race arbitration among the buses connected to the CBG to select a winner bus for a time slot, and selectively forwarding data received at the CBG from the winner bus to a destination bus in the time slot based on whether the winner bus or the destination bus has a connection to an external network with respect to the application network and whether a communications device connected to the winner bus or the destination bus performs a critical function. Other embodiments are also described.

Abstract: An integrated circuit package for an integrated circuit having one or more sensor elements in a sensor element area of the circuit. An encapsulation covers bond wires but leaves an opening over the sensor element area. A protection layer is provided over the integrated circuit over which the encapsulation extends, and it has a channel around the sensor element area to act as a trap for any encapsulation material which has crept into the opening area.

Abstract: Disclosed is a temperature sensor (200) comprising a p-n junction device (110), a current device (120, 130) adapted to provide a sequence of different currents to the p-n junction device, a measurement circuit adapted to measure the voltage characteristics of the p-n junction device as a function of said sequence, and a processor adapted to determine the minimum value of the voltage swing from said characteristics and to convert said minimum value to a temperature value. A method of measuring a temperature using such a device is also disclosed.

Abstract: Systems and methods for encoding a slot table for a communications controller of a communications network are described. In one embodiment, a method for encoding a slot table for a communications controller of a communications network includes classifying branches of the communications network that are connected to the communications controller into at least one group, where each of the at least one group includes multiple branches, and generating a slot table entry for a time slot for accessing the communications network through the communications controller based on the at least one group. Other embodiments are also described.

Abstract: An apparatus for misalignment compensation in optical joysticks is described. The optical joystick includes a light source, a plurality of photodetectors, and circuitry for controlling operation of the optical joystick. In some embodiments, each of the photodetectors may partitioned into a plurality of photodetector elements and select photodetector elements are configured to be individually activated in order to cause an electrical shifting of the selected photodetector elements to achieve a different operational alignment position of optical components of the optical joystick. In some embodiments, the light source may be similarly be calibrated by individually activating portions of a light-source array to cause an electrical shift. Various other embodiments and methods of operation are also described.

Abstract: An invention for generating a slot table entry address for a communications device of a communications network includes a method that involves processing a slot counter value according to a configuration setting value to produce a processed slot counter value, the slot counter value identifying a time slot of data communications of the communications network, masking a cycle counter value according to the configuration setting value to generate a masked cycle counter value, where the cycle counter value identifies a communications cycle containing the time slot, and processing the processed slot counter value and the masked cycle counter value to generate a slot table entry address such that a corresponding slot table entry of the time slot of the communications cycle in a slot table is accessed by the communications device at the slot table entry address.

Abstract: Systems and methods for testing a communications network having a central bus guardian (CBG) to detect a faulty condition associated with the CBG are described. In one embodiment, a method for testing a communications network having a CBG to detect a faulty condition associated with the CBG includes supplying a communications schedule to the CBG, causing test data to be transmitted between different buses that are connected to the CBG according to the communications schedule, and determining the faulty condition associated to with the CBG based on whether or not the test data is received according to the communications schedule. Other embodiments are also described.

Abstract: Methods, devices and circuits are provided for protection from backdrive current. One such device is subject to back voltage from an output node of the device and includes circuitry that is configured to compare the supply voltage node and the output node. In response to the comparison, the circuitry generates an output signal. Level shifted versions of the output signal are used to provide an output voltage corresponding to the higher of a supply voltage node and an output node. Switches are used to place the device in different modes in response to the output signal.

Abstract: An RF receiver comprising: an amplifier configured to receive an RF signal over an input bandwidth and to provide an amplified RF signal; an equalizer circuit connected to the amplifier to receive the amplified RF signal and configured to provide an equalized RF signal; a converter module connected to the equalizer circuit and comprising an analog to digital converter configured to convert the equalized RF signal to a digital signal; and a digital signal processing module connected to the receiver module and configured to process the digital signal to provide a plurality of channels at an output of the receiver, wherein the digital signal processing module is further configured to process the digital signal to determine a measure of tilt in the RF signal across the input bandwidth and is connected to the equalizer circuit to provide a control signal for adjusting the measured tilt.