Abstract: A thermally-compensated oscillator has a current reference with an output current which relates to an ambient temperature with a first relationship, a ring oscillator having an operating frequency which relates to the ambient temperature with a second relationship, and which receives the output current of the current reference and outputs an oscillator signal, and a level shifter which receives the oscillator signal from the ring oscillator and outputs a corresponding voltage-regulated clock signal.

Abstract: The invention relates to a first network device outputting content, the first network device retrieving an address of a second network device using a contactless interface from a third device, and the first network device transmitting the content, which was output at the time of retrieving said address, to the second network device.

Abstract: A sensor module (130) for a catheter (110), the sensor module (130) comprising a biofilm detection unit (131) adapted for detecting a characteristic of a biofilm (132) and electric circuitry (135, 800) for providing an output signal indicative of a result of the detection.

Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing two parts (13, 14) comprising electrically insulating material such as plastic; providing members (21, 22, 23) comprising electrically conductive material; providing a microelectronic device (30); positioning the electrically conductive members (21, 22, 23) and the microelectronic device (30) on the electrically insulating parts (13, 14); and placing the electrically insulating parts (13, 14) against each other, wherein the microelectronic device (30) and portions of the electrically conductive members (21, 22, 23) are sandwiched between the electrically insulating parts (13, 14). The electrically conductive members (21, 22, 23) are intended to be used for realizing contact of the microelectronic device (30) arranged inside the package (1) to the external world.

Abstract: The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate (2) comprising the bottom electrode (10), providing on the substrate a dielectric layer (4) comprising a recess (7) containing the metal for forming the resistive layer (11), providing on the substrate a dielectric layer (5) comprising an opening (8) exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.

Abstract: One embodiment of the present application includes the preparation of an assertion for inclusion in an integrated circuit simulation performed with a processing device (21). In response to an input to this processing device (21), a set of integrated circuit waveforms are defined to test the assertion. The processing device (21) tests the assertion with these waveforms; and after successful testing, the integrated circuit simulation is performed with the assertion.

Abstract: A bulk-acoustic-mode MEMS resonator has a first portion with a first physical layout, and a layout modification feature. The resonant frequency is a function of the physical layout, which is designed such that the frequency variation is less than 150 ppm for a variation in edge position of the resonator shape edges of 50 nm. This design combines at least two different layout features in such a way that small edge position variations (resulting from uncontrollable process variation) have negligible effect on the resonant frequency.

Abstract: A method of synchronising the reference clock of a first wireless device with a master reference clock of a second wireless device via a wireless network. The method involves transmitting, from the second wireless device to the first wireless device, a dedicated synchronisation frame via a dedicated synchronisation channel; receiving the dedicated synchronisation frame at the first wireless device; and synchronising the reference clock of the first wireless device with the master reference clock of the second wireless device based on the received dedicated synchronisation frame.

Abstract: PCB or similar material is used for stiffener rings supporting heat sinks in Flip Chip Ball Grid Array (FCBGA) packages. The substrate material of the package and the stiffener ring share the same or similar Coefficient of Thermal Expansion. Stiffener rings may be manufactured from PCB or similar material using a router.

Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

Abstract: The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940). Via connections (920) are provided in trenches that go through the whole thickness of the wafer.

Abstract: In order to provide a bus guardian (30) for monitoring communication between and among a number of nodes (100), in particular between and among a number of electronic control units, the bus guardian (30) being designed for monitoring at least one cyclic time-triggered communication media access schedule for transmitting messages between and among the nodes (100) across at least one communication media (10), in particular across at least one channel (12) and across at least one optional further channel (14), and being assigned to at least one communication controller (40), the communication controller (40) comprising the communication media access schedule, wherein the bus guardian (30) as well as a corresponding method require neither any a priori knowledge of the communication schedule nor any configuration parameter and monitor the communication media access schedule of the communication controller (40) even during start-up of the communication, it is proposed that that the bus guardian (30) is able to lear

Abstract: The invention relates to an integrated Doherty amplifier with an input network connecting the input to the main stage and to the peak stage, and with an output network connecting the main stage and the peak stage to the output. The output network has a shunt capacitor to signal-ground in parallel to a parasitic capacitance of the main stage, and has a shunt inductor between the main stage and signal ground. The shunt configuration enables to use the MMIC Doherty amplifier in a wide frequency range. At least some of the inductors of the input network and/or output network are implemented using bond wires. Their orientations and locations provide minimal mutual electromagnetic coupling between the wires and the return RF current paths.

Abstract: A planar extended drain transistor (100) is provided which comprises a control gate (102), a drain region (109), a channel region (107), and a drift region (108), wherein the drift region (108) is arranged between the channel region (107) and the drain region (109). Furthermore, the control gate (102) is at least partially buried into the channel region (107) and the drift region (108) comprises a doping material density which is lower than the doping material density of the drain region (109).

Abstract: In one aspect of the invention, a method provides a calibrated critical-failure model for a printing process of a critical feature by virtue of a classification of an optical parameter space according to at least two print-criticality levels. Print failure of a respective critical feature is judged on the basis of a print-failure criterion for the critical feature. The respective print-criticality level is ascertained from test-print-simulation data at a sampling point of a process window for a given point in an optical-parameter space, and from a failure rule. An advantage achieved with the method is that it comprises ascertaining the predefined optical-parameter set from the test-print-simulation data at only one sampling point of the process window, which sampling point is identical for all test patterns. This saves processing time and processing complexity by reducing the number of ascertained optical-parameter sets and their processing in the subsequent scanning and classifying steps.

Abstract: A method of forming a field effect transistor comprising a gate formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone and lateral zones in the length of the gate, the method comprising forming a gate comprising a portion of insulating layer, a portion of semiconducting layer formed over the insulating layer, and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the center of the gate remains; and reacting the semiconducting gate with a metal deposited over the gate.

Abstract: Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a first clock having a first clock frequency (f1) with a first clock frequency tolerance (?f1), and a second timing engine that samples bits received by the receiver with a second clock having a second clock frequency (f2) with a second clock frequency tolerance (?f2). The second clock frequency is less than the first clock frequency. The network receiver may also include a third timing engine that samples bits received by the receiver with a third clock having a third clock frequency (f3) with a third clock frequency tolerance (?f3). The third clock frequency may be greater than the first clock frequency.

Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.

Abstract: A sigma-delta modulator (200) for an ADC, passes an input signal to a loop filter (20), then to a multi-bit quantizer (30) of the modulator (200). An output of the quantizer (30) is passed to a digital filter (50), and a feedback signal is passed back to the loop filter (20), the feedback signal having fewer bits than are produced by the multi-bit quantizer (30). No separate feedback loop for the digital filter (50) is used, so as to reduce the need to adjust the loop filter for stable operation. The digital filter (50) can have an order greater than one in the passband of the sigma-delta modulator (200).

Abstract: A system and method for synchronizing otherwise independent oscillators private to I2C Bus slave devices. An I2C Bus master device can issue two new general call commands, CALIBRATE and ZERO COUNTERS. The I2C Bus slave devices respond to the CALIBRATE command by counting the number of cycles its local, private oscillator makes through during the communication transfer period of the CALIBRATE command on the I2C Bus. All such I2C Bus slave devices measure the same communication transfer period on the I2C Bus, so the differences in the digital measurements obtained by each of them are proportional to their respective oscillator frequencies. The digital measurements are privately used by each I2C Bus slave device to calculate appropriate oscillator prescale factors, and to automatically load the values that will harmonize the final product frequencies of all of the local oscillators on all of the I2C Bus slave devices in the system.