Abstract: A power supply circuit and a method for operating the power supply circuit are described. In one embodiment, a power supply circuit includes at least one input terminal to receive at least one input voltage, a power element including multiple power element components configured to convert the at least one input voltage to at least one output voltage, multiple regulator controllers configured to control the power element components for the conversion of the at least one input voltage to the at least one output voltage, at least one first switch coupled to the regulator controllers and the power element components, and multiple output terminals to output the at least one output voltage. The at least one first switch is used to configure the power supply circuit to function as either one voltage regulator or multiple independent voltage regulators. Other embodiments are also described.

Abstract: In a method of processing data, an RFID signal (6) sent by a reader (3,5) via a field generated by the reader (3,5) is received at a passive RFID transponder (2). The transponder (2) comprises a dedicated receiver (28) for receiving a time signal (8), which is wirelessly sent By an external sender (4) and comprises information about the present time. The transponder (2) including the dedicated receiver (28) is powered utilizing the field such that the dedicated receiver (28) detects the time signal (8) and decodes the present time. Utilizing the transponder (2), the first data (7) contained in the RFID signal (6) is decoded and processed. Second data (9) which are time stamped by said transponder (2) utilizing said present time are generated, and a response signal (10) comprising the second data (9) is transmitted from the transponder.

Abstract: A method of transferring content between at least two devices, the devices being capable of outputting said content, and a device itself is disclosed. First, the devices are connected via associated interfaces. Then, there is a detection or negotiation which of the devices is currently outputting content. Finally, content, which is currently being output, is transferred from the corresponding outputting device or devices to the other device or devices via the interfaces.

Abstract: This invention relates to a semiconductor device for testing and analyzing integrated circuits (1) on a first side and a second side. The semiconductor device (1) having a first surface (A1) and a second surface (A2) both sides having a set of contacts (P3a, P3b, P3a?, P3b?). The sets of contacts on are symmetrically located on positions relative to a first fictitious plane of symmetry (S1) and a second fictitious plane of symmetry (S2). The semiconductor device (1) has at least a first position of use and a second position of use, whereby the second position of use is obtained by rotating the semiconductor device (1) in the first position of use 180° around a fictitious axis (M). This axis (M) is defined by the crossing of the first fictitious plane of symmetry (S1) and the second fictitious plane of symmetry (S2). The semiconductor device thus obtained provides a flexible and generic solution for testing and analyzing integrated circuits on both sides.

Abstract: The invention relates to a read only magnetic information carrier (1b, 1c, 1d) comprising a substrate (2), an information layer (3) and a stabilizing layer (15a, 15b). The information layer (3) comprises a pattern of magnetic bits (4) of magnetic material wherein the pattern of magnetic bits (4) constitutes an array of bit locations. The presence or absence of the magnetic material at a bit location represents a value of the bit location by a magnetic field (5) having a predetermined magnetization direction (6). The stabilizing layer (15a, 15b) is arranged between the substrate (2) and the information layer (3) and comprises hard magnetic material (8, 9) which is magnetically coupled to the magnetic material of the magnetic bit (4). The magnetically coupled hard magnetic material (8, 9) provides the predetermined magnetization direction (6) of the magnetic field (5).

Abstract: An RFID communication system comprises an NFC device (11) and a smart card (2) with contactless card functionality, wherein the NFC device (11) and the smart card (2) are couplable to each other via a protocol converter (7), wherein the NFC device (11) is coupled to an antenna (3) to receive electromagnetic signals (ES) from an RFID reader/writer and to transmit response signals (RS) to the RFID reader/writer by modulating received electromagnetic signals (ES). The electromagnetic signals (ES) contain first and second characteristic components (FE, RE) which define the begin and the end of a predefined signal pattern (PA), wherein the second characteristic component triggers a predefined response delay time (FDT) at the expiration of which the RFID communication system has to respond to the RFID reader/writer. A device (12) for compensating signal delays is provided that comprises signal pattern shortening means (13).

Abstract: A Microprocessor (1) in a security-sensitive computing system for processing an operand according to an instruction is for improving its security provided with a modulo-based check hardware (2) to perform operations in parallel to the microprocessor (1) and for comparing both results regarding congruence.

Abstract: A method and system for determining and compensating for a non-linearity in a hands-free acoustic telecommunication device is disclosed. The method determines a back electromotive force signal induced in a loudspeaker from at least one of a coil voltage, a current signal and estimates of coil resistance and inductance, estimating at least one of a cone position and a cone velocity from the BEMF integrated with respect to time and determining an estimate of an echo value from a series connection of an estimated inverse of a force factor function primitive and the estimated acoustic impulse response; and outputting the estimated echo value.

Abstract: A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).

Abstract: A reader device for detecting the presence of a transponder within an operating distance of the reader device, the reader device comprising a resonant circuit adapted for generating an electromagnetic field having a frequency distribution around a resonance frequency, and a transponder detection unit adapted for detecting the presence of the transponder within the operating distance of the reader device by a shift of the resonance frequency of the resonant circuit in the presence of the transponder within the operating distance of the reader device.

Abstract: A method of inventorying data carriers (2) by means of a communication station, whereby the communication station and each data carrier (2) are brought into communicative connection, and each data carrier (2) brought into communicative connection with the communication station is capable of generating a response signal (IDS) that renders possible an inventorying of the data carrier and is capable of delivering a generated response signal (IDS) with the use of a transmission start moment that can be selected from a plurality of transmission start moments (t5, t6), each data carrier tests whether another data carrier (2) is already giving its response signal (IDS). Each data carrier (2) subsequently discontinues the generation or delivery of its response signal (IDS) if another data carrier (2) is already providing its response signal (IDS).

Abstract: An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections.

Abstract: A method for improvement of contrast in an image shown on a display having a range of displayable video levels. The method comprises providing input video levels representing the image, said levels being within said displayable range; providing a transfer function (120, 121) having a slope greater than one everywhere in a gain region (130) of said displayable range, and a slope greater than zero and less than one everywhere in a softclip region (131) of said displayable range, said regions (130, 131) meeting at a threshold level (125), the transfer function (120, 121) being adapted to transfer any input video level within said displayable range to an output level within displayable said range; and transforming said input levels into output levels within said range, using the transfer function (120, 121). According to the invention, instead of “hardclipping” there is a “softclipping” of levels. Hence, compared to conventional methods, a higher gain may be used.

Abstract: A frequency conversion circuit configured to mix a first input signal (RF+,RF?) at a first frequency with a second input signal (LO+,LO?) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules, each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF?) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO?); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF?) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.

Abstract: The invention provides a LED arrangement including a LED string of a series arrangement of LED segments. A LED segment includes a single LED or a series arrangement of LEDs. A switching element (12, 22) is arranged in parallel with each corresponding LED segment (10, 20) of the LED string, for controlling a current (52, 62) through the LED segment (10, 20). A capacitor (13, 23) is arranged in parallel with each corresponding LED segment (10, 20) in order to prevent the occurrence of possibly harmful current spikes while switching one or more LED segments. The LED arrangement may also include a switched-mode power supply (2001). The invention further provides a LED assembly. A plurality of such LED assemblies assembles easily into a LED arrangement according to the invention.

Abstract: The present invention relates to a gigitaol phaselocked loop DPLL (300, 400) having a phase-to-digital P2D (60) with an enhanced bang-bang phase detector BBPD. Such a P2D (60) comprises a BBPD (62), an additional digital circuit (200) including a sign detector (210), a counter (220) and a mapping function (230), and a summer block (64). During the locking process, the BBPD (62) may-output a repeating value, namely a string of data bits of same polarity value either “+1” or “?1”. The polarity sign is detected by the sign detector (210), and the data string length is determined by the counter (220) that is reset to zero whenever the BBPD output changes sign. The mapping function (230) is configured for mapping the data string length in input to the phase correction level in output Its output is added to that of the BBPD (62) through the summer block (64), such that the phase correction level is increased to enhance the locking process whenever a data string is detected.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. The power transistor circuitry, the broadband combiner, and the impedance matching filter are integrated in a unified package. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described.

Abstract: A method and system for accessing memory using an auxiliary memory is presented. According to the invention store and following load instructions accessing same memory locations are identified and a temporal difference is determined. The store instructions comprise an indication for the time interval lapsing until a data element, which is stored by the store instructions, is loaded by a load operation for the first time. Based on this indication the store instruction is given access directly to the main memory or is routed to main memory through an auxiliary memory.

Abstract: A sensor (400) for sensing jitter in a clock signal has a DLL (402, 310, 312) for locking a clock signal and a delayed version of the clock signal. The sensor comprises a delay line (402) having a first number of cascaded controllable delay segments. The DLL uses a second number of the cascaded delay segments for generating a delay of an average clock period of the clock signal. The second number is smaller than the first number. The sensor also has a comparator (408) for supplying a sensor output signal representative of a comparison of the clock signal and a further delayed version of the clock signal. The further delayed version of the clock signal is obtained from an output of a specific one of the delay segments located in the delay line after the second number of cascaded delay segments.

Abstract: The system and method of the present invention provide a single mixer (200-400) with significantly reduced noise performance at a low cost by adding a current control circuit (109) that reduces the current in at least the switching stage (103, 303, 403) during polarity changes of the local oscillator (LO) signal (104). Alternative embodiments (300-400) are provided for a single mixer having significantly reduced noise wherein the low-noise characteristic is enhanced by a further modification to the switching stage (303-403).