Abstract: A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick gate electrode and the integral first layer also provides a first part of a stack of materials which constitute a thick trench sidewall insulating layer for a thin field plate. Consistent with an example embodiment, there is a method of manufacture. A hardmask used to etch the trenches is removed before providing the silicon dioxide layer. The layer is then protected by successive selective etching of the oxide layer and the nitride layer in the upper parts of the trenches. After the gate electrodes are provided, layers for the channel accommodating regions and source regions may be formed through the oxide layer on the upper surface.

Abstract: A signal processing method for enhancing the dynamic range of a signal is disclosed. The method comprises: a) forming an attenuated signal from an input signal; b) filtering each of the input and the attenuated signals such that the sum of their bandwidths is less than or equal to the bandwidth of a transmission channel; c) modulating a first one of the filtered input signal and the filtered attenuated signal, whereby the filtered input signal and the filtered attenuated signal occupy respective non-overlapping frequency ranges within the bandwidth of the transmission channel; and d) combining the modulated signal with the second one of the filtered input signal and the filtered attenuated signal to form a composite output signal.

Abstract: A processing device having a housing includes first communication device for receiving and/or transmitting an information signal and processor for processing the information signal received and/or to be transmitted, as well as second communication device for the contactless retrieval of control information stored in a data carrier which is detachably connected to the of the processing device, which processing of the information signal by the processing device can be influenced with the aid of the retrieved control information.

Abstract: Presented is an interface circuit for connecting a RF antenna to a RF device.

Abstract: Various embodiments relate to a receiver and a timing circuit for synchronization between a transmitter clock of an MPEG stream and the local system clock of a receiver. The timing circuit may implement a phase-locked loop (PLL) circuit with a MD controller to produce a control signal based on the difference between the transmitter reference clock and the local system clock. Various embodiments may use clock differential signals and an accumulated error signal to produce proportional, integral, and derivative output components for a control signal. The control signal may control a signal generator that adjusts the frequency and/or phase of the local signal clock to lock with the transmitter reference clock. Various embodiments may also include an outlier filter to remove error signals outside a defined range and/or a programmable system clock to add precision to the generated local system clock.

Abstract: An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD protection circuit includes a diode-type circuit having a p-n junction that exhibits a low breakdown voltage. Connected in series with the diode between an internal node susceptible to an ESD pulse and ground, are regions of opposite polarity having junctions therebetween for mitigating the passage of leakage current via voltage sharing with the diode's junction. Upon reaching the breakdown voltage, the diode shunts current to ground via another substrate region, bypassing one or more junctions of the regions of opposite polarity and facilitating a low clamping voltage.

Abstract: The invention relates to a method of manufacturing integrated circuits and in particular to the step of forming shallow trench isolation (STI) zones. The method according to the present invention leads to electronic devices and to integrated circuits having reduced narrow width effect and edge leakage. This is achieved by performing an extra implantation step near the edge of the STI zone, after formation of the STI zones.

Abstract: A basic symmetric ?/2 phase-detector receives four control signals that control a differential current at the detector's output. Each respective control signal is a linear combination of a respective pair of signals chosen from a first input signal, its logic complement, a second input signal and the logic complement of the latter. Operation is based on time-averaging the differential current, the result being zero at a phase difference of ?/2. By means of adding one or more additional current sources to the output, controlled by one or more of the control signals, the basic operation is skewed. The time-averaged output current is now made zero only at a value of the phase difference different from ?/2. In an embodiment with uniform current sources and resistors, the modified detector is configured for a phase difference of ?/2N .

Abstract: A finFET structure is made by forming a fin (14), followed by a gate stack of gate dielectric (16), metal gate layer (18), polysilicon layer (20) and silicon-germanium layer (22). The gate stack is then patterned, and source and drain implants formed in the fin (14) away from the gate. The silicon germanium layer (22) is selectively etched away, a metal deposited over the gate, and silicidation carried out to convert the full thickness of the polysilicon layer (20) at the top of the fin. A region of unreacted polysilicon (38) may be left at the base of the fin and across the substrate.

Abstract: A planar inductor (50) comprises a conductive path in the form of a spiral pattern (53A-53D, 54A-54D). A conductive connecting path (62A, 63) connects a terminal (60) to an intermediate tap point (61A). The connecting path comprises at least one path portion which is radially directed with respect to the spiral pattern (53A-53D). The connecting path (62A, 63) can be routed via the inside of the spiral pattern. Where the connecting path comprises only radially-directed path portions, they are commonly joined at the center (64) of the spiral pattern. Multiple path portions (62A, 62B) can each connect to the intermediate tap point of a respective conductive path. The connecting path can use a further conductive track (85) which is parallel to the conductive path which forms the spiral pattern.

Abstract: The package comprises a chip and a plurality of frame contact pads. The chip is attached to the frame contact pads in a die attach area with a die attach adhesive. The chips is coupled to frame contact pads outside the die attach area with connecting elements. The chip, the connecting elements and the frame contact pads outside the die attach area are anchored in an electrically insulating encapsulation. The frame contact pads each comprise a first patterned layer and a second patterned layer, which second layer has the surface that is exposed outside the encapsulation. At least a portion of the frame contact pads in the die attach area has a first patterned layer with a first pattern that comprises at least one flange/lead that is outside the second patterned layer when seen in perpendicular projection of the first layer on the second layer.

Abstract: Apparatus for regulating the temperature of a light emitting diode (LED). The apparatus includes a heat sink, an LED mount, and an LED mounted on the LED mount. The LED mount is configured to change shape in response to a change in temperature. The change in shape alters the position of the LED relative to the heat sink, for adjusting heat transfer between the LED and the heat sink. The LED mount may include a laminated portion such as a bi-metallic strip.

Abstract: An extended drain transistor (100) comprising a substrate (101), a gate (103) formed on the substrate (100), the gate (103) having a first side wall (104) and a second side wall (105) opposing the first side wall (104), an extended drain (106) implanted in a surface portion of the substrate (101) adjacent the second side wall (105) of the gate (103), a spacer (107) on the second side wall (105) of the gate (103), a source (108) implanted in a surface portion of the substrate (101) adjacent the first side wall (104) of the gate (103), and a drain (109) implanted in a surface portion of the substrate (101) adjacent the spacer (107) in such a manner that the extended drain (106) is arranged between the gate (103) and the drain (109).

Abstract: Present invention relates to an electrostatic discharge protection circuit for a transistor circuit having electrostatic discharge protection circuits coupled to an input and to an output terminal. The protection circuits comprise delay means having a predetermined delay time and switchable connecting means connected between said input terminal and a control terminal of said transistor circuit. The delay means are configured for activating said switchable connecting means for said predetermined delay time in response to an electrostatic discharge at said input terminal.

Abstract: This invention relates to a method, a computer program product, a device, and a system, wherein a receiver unit is configured to operate in a single-channel mode and in a multi-channel mode, wherein in the single-channel mode the receiver unit is configured to output exactly one channel of a received signal, and in the multiple-channel mode the receiver unit is configured to output at least two channels of the received signal.

Abstract: Various embodiments relate to a pressure sensor and related methods of manufacturing and use. A pressure sensor may include an electrical contact included in a flexible membrane that deflects in response to a measured ambient pressure. The electrical contact may be separated from a signal path through a cavity formed using a sacrificial layer and PVD plugs. At one or more defined touch-point pressure thresholds, the membrane of the pressure sensor may deflect so that the state of contact between an electrical contact and one or more sections of a signal path may change. In some embodiments, the change of state may cause the pressure sensor to trigger an alarm in the electrical circuit. Various embodiments also enable the operation of the electrical circuit for testing and calibration through the use of one or more actuation electrode layers.

Abstract: A method is disclosed of manufacturing a vertical transistor which comprises providing a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region; forming a trench in said substrate, said trench at least partially extending into said vertical stack of regions; lining said trench with a stack comprising a gate dielectric liner, an etch protection layer and a further insulating layer; filling the remainder of the trench with a shield electrode material; exposing a top portion of the shield electrode material by removing the further insulating layer to a first depth in said trench; forming a inter electrode dielectric on the exposed shield electrode material; removing the etch protection layer to the first depth from said trench; and forming a gate electrode in said trench between the inter electrode dielectric liner and the exposed portion of the gate dielectric liner.

Abstract: A bipolar transistor is fabricated having a collector (52) in a substrate (1) and a base (57, 58) and an emitter (59) formed over the substrate. The base has a stack region (57) which is laterally separated from the emitter (59) by an electrically insulating spacer (71). The insulating spacer (71) has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a ?-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.

Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.

Abstract: With an RFID system for communicating between reading units (R1, R2) and transponders (T1, T2) in at least two different scan areas (S1, S2), wherein at least one reading unit (R1, R2) and at least one antenna (A1-A4, B1-B4) communicating with the reading unit are allocated to each scan area (S1, S2) for the radiation of electromagnetic signals (EA1-EA4, EB1-EB4) in the scan area (S1, S2), the antennas (A1-A4, B1-B4) are designed in such a way that at least one antenna (A1, A3) of a scan area (S1) has a different polarization and/or a different polarization rotation direction relative to at least one antenna (B2, B4) of another scan area (S2).