Patents Assigned to NXP
  • Publication number: 20120232964
    Abstract: The invention relates to a road toll system using a vehicle-mounted satellite navigation receiver, from which routes taken and road prices incurred are determined. A billing system bills a user in dependence on the road prices incurred. A portable activation device transmits information concerning the owner of the portable activation device to the vehicle-mounted unit, and the vehicle-mounted unit provides information to the billing system to enable identification of the owner of the portable activation device. In combination, the portable activation device and the vehicle-mounted unit can be considered to function in a similar way to a known vehicle-mounted OBU. However, by separating the data necessary to provide user-personalisation into the portable activation device, the vehicle-mounted unit can become more standard, and the user is able to drive other vehicles more easily.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 13, 2012
    Applicant: NXP B.V.
    Inventor: Jan Rene BRANDS
  • Patent number: 8261997
    Abstract: A carrier assembly for receiving an RFID transponder chip has an attachment side for being attached to a consumer device and an operation side for receiving an RF signal in operational use of the RFID transponder chip.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventor: Michael Gebhart
  • Patent number: 8263471
    Abstract: A method of producing a multilayer structure is provided, wherein the method comprises forming a phase change material layer onto a substrate, forming a protective layer, forming a further layer on the protective layer, patterning the further layer in an first patterning step, patterning the protective layer and the phase change material layer by a second patterning step. In particular, the first patterning step may be an etching step using chemical etchants. Moreover, electrodes may be formed on the substrate before the phase change material layer is formed, e.g. the electrodes may be formed on one level, e.g. may form a planar structure and may not form a vertically structure.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Romain Delhougne, Judit Lisoni, Vasile Paraschiv
  • Patent number: 8264235
    Abstract: The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non-defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Dirk Kenneth De Vries, Roberto Maurizio Gonella
  • Patent number: 8264092
    Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • Patent number: 8265265
    Abstract: In order to further develop a circuit arrangement for as well as a method of performing at least one operation, in particular at least one cryptographic calculation, wherein the problem of creating at least one key, in particular the R[ivest-]S[hamir-]A[dleman] key, satisfying at least one defined digital signature laws, in particular satisfying the German Digital Signature Law, is solved it is proposed that at least one, preferably two, prime numbers (p; q) for key generation, in particular for R[ivest-]S[hamir-]A[dleman] key generation, are searched in compliance with at least one defined digital signature law, in particular with the German Digital Signature Law.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventor: Sander Matthijs Van Rijnswou
  • Patent number: 8264801
    Abstract: Power supplies are switched in a manner that mitigates parasitic shorts. According to an example, a control circuit (e.g., 310) operates primary and backup power supplies using the higher of the primary and backup supply voltages, for switching between the power supplies.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Friedbert Riedel, Giovanni Genna
  • Patent number: 8266346
    Abstract: A data processing apparatus receives a communication signal that contains temporally successive bits. A programmable processor circuit executes a plurality of series of programmed instructions for operations such as parity checking, each at a time of reception of a respective one of the bits. The processor circuit suspends operation each time after executing a respective one of the series of instructions. A synchronization circuit triggers execution of respective ones of the series, each time at the time of reception of the respective one of the bits, and, except for a last one of the series, prior to reception of one or more later bits that contribute to the data word.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Franciscus Johannes Klosters, Patrick Willem Hubert Heuts, Joris Rudolf Beverloo, Hendrik Bernard Heule
  • Patent number: 8266369
    Abstract: Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit and to provide access to the stored data. An interface controller communicates with the flash memory circuit via the peripheral interface bus to initialize the flash memory circuit and to access data thereto, in response to requests from a processor. In some applications, the flash memory circuit is initialized by sending commands to it. The interface may be placed into a read-only mode in which data in the flash memory is accessed as part of main (computer) processor memory, using the FIFO to buffer data from the flash.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Craig MacKenna, Prithvi Nagaraj, Rob Cosaro
  • Patent number: 8265160
    Abstract: Various exemplary embodiments relate to a method and related motion estimation unit for performing motion estimation on video data comprising a plurality of frames. The method may begin by reading a current frame of the plurality of frames from a memory of a motion estimation unit. The method may then select a motion vector for each respective block of pixels in a current row of the current frame. The step of selecting the motion vector may include, for each respective block, selecting, by the motion estimation unit, a candidate vector for at least one block directly surrounding the respective block based on a determination of whether the directly surrounding block has been processed for the current frame, calculating, for each candidate vector, a difference value, and selecting, as the motion vector, the candidate vector with the lowest difference value.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Ghiath Al-Kadi, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Abraham Karel Riemens, Klaas Brink
  • Patent number: 8263430
    Abstract: A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterized in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alky
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: September 11, 2012
    Assignees: NXP B.V., Freescale Semiconductor, Inc.
    Inventors: Janos Farkas, Lynne M Michaelson, Srdjan Kordic
  • Patent number: 8266360
    Abstract: An electronic circuit has an interface for an I2C-bus. The interface comprises a first node for a clock line of the I2C-bus; a second node for a data line of the I2C-bus; and an I2C-bus controller for controlling an operation of the interface under combined control of the clock line and the data line. The circuit has a plurality of further nodes for connecting to a plurality of further data lines. The controller has an operational mode for control of receiving from the further nodes, or for control of supplying to the further nodes, a plurality of data bits in parallel under combined control of the clock line and the data line.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventor: Sandeep Agrawal
  • Patent number: 8264678
    Abstract: A light sensor and light sensing system to detect an intensity of incident light and an angle of incidence of the incident light. The light sensor includes a dielectric layer, a plurality of photo detectors coupled relative to the dielectric layer, and a plurality of stacks of opaque slats embedded within the dielectric layer. The dielectric layer is substantially transparent to the incident light. The photo detectors detect the incident light through the dielectric layer. The stacks of opaque slats are approximately parallel to an interface between the dielectric layer and the photo detectors. The stacks of opaque slats define light apertures between adjacent stacks of opaque slats. At least some of the stacks of opaque slats are arranged at a non-zero angle relative to other stacks of the opaque slats.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Vitali Souchkov, Rob Van Dalen, Padraig O'Mathuna
  • Patent number: 8265180
    Abstract: A system, device and method are described for suppressing certain sub-carrier frequencies within a multi-path transmission system and efficiently notifying a receiver (400) of the suppressed sub-carriers. In various embodiments of the invention, an OFDM system uses the preamble (210) of an OFDM burst for indicating which sub-carrier frequencies are being suppressed by a transmitter (300).
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventor: Charles Razzell
  • Publication number: 20120226873
    Abstract: A multiprocessor arrangement is disclosed, in which a plurality of processors are able to communicate with each other by means of a plurality of time-sliced memory blocks. At least one, and up to all, of the processors may be able to access more than one time-sliced memories. A mesh arrangement of such processors and memories is disclosed, which may be a partial or complete mesh. The mesh may to two-dimensional, or higher dimensional. A method of communication between processors in a multiprocessor arrangement is also disclosed, in which one or more processors are able to each access a plurality of memories, in each case by time-slicing.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 6, 2012
    Applicant: NXP B.V.
    Inventors: Francisco Barat Quesada, Mark Janssens
  • Publication number: 20120223862
    Abstract: A multiband antenna comprising a substrate having first and second surfaces. A first conductive plate located on the first surface comprises a first conductive region couplable to ground by a shorting element, and a second conductive region. The first and second conductive regions are located to define a gap therebetween. The antenna also has a second conductive plate on the substrate's second surface. The second conductive plate is coupled to a signal terminal of a feeding port and positioned to provide capacitance with the first conductive region. The antenna also has a third conductive plate on the substrate's second surface. The third conductive plate is positioned to provide capacitance with the second conductive region, and a connecting conductor configured to electrically couple the third conductive plate to the second conductive region.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 6, 2012
    Applicant: NXP B.V.
    Inventor: Anthony KERSELAERS
  • Publication number: 20120223864
    Abstract: A multiband antenna (200) comprising a substrate (202) and at least one conductive plate (204) on the substrate (202). The at least one conductive plate (204) defines a first conductive region (206), a second conductive region (208) and a third conductive region (210). The first, second and third conductive regions (206, 208, 210) are configured so as to define a first gap (212) between the first conductive region (206) and the second conductive region (208); and a second gap (214) between the second conductive region (208) and the third conductive region (210). The multiband antenna also comprises a feeding port (230) comprising a signal terminal (230a). The signal terminal (230a) is configured to couple the second conductive region (208) to a first connecting element for conducting transmit or receive signals.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Applicant: NXP B.V.
    Inventor: Anthony KERSELAERS
  • Publication number: 20120223863
    Abstract: A multiband antenna comprising a substrate having first and second surfaces. A first conductive plate is provided on the first surface and a second conductive plate is provided on the second surface. The second conductive plate at least partially overlaps the first conductive plate in the plane of the substrate. The antenna also comprises a ground plane, wherein the substrate is connected to and is substantially perpendicular to the ground plane, and a feeding port (412) that is electrically coupled to both the first and second conductive plates. The first conductive plate is configured to transmit or receive signals in a first frequency band and the second conductive plate (408) is configured to transmit or receive signals in a second frequency band.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Applicant: NXP B.V.
    Inventor: Anthony Kerselaers
  • Publication number: 20120223809
    Abstract: A transponder for wirelessly receiving external data and for monitoring access to application data, the transponder including: a data storage storing application data; a data storage control region; and a data storage access controller configured to store, in the data storage control region, data indicative of an access to the application data stored in the data storage, when the application data was accessed based on the external data. Further, a method and a reader for monitoring access to application data stored in a transponder are described.
    Type: Application
    Filed: February 29, 2012
    Publication date: September 6, 2012
    Applicant: NXP B.V.
    Inventor: Mario Steiner
  • Patent number: 8257506
    Abstract: The present invention relates to a cost saving liquid-treatment unit (100). According to the invention, a control unit (152), which is connected to an input port of a control valve (118, 120, 122), is adapted to set, in dependence on the evaporation rate of a treatment liquid on the substrate at the given or desired temperature of the substrate and/or at the given or desired pressure of a gaseous ambient atmosphere at the substrate, a number of dispense pulses to be applied to the substrate for the liquid treatment, a respective pulse duration of individual dispense pulses, and respective dispense-interruption time spans between the individual dispense pulses. This way, the use of treatment liquid is reduced to a minimum amount, thus reducing costs for providing and cleaning treatment liquid.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: September 4, 2012
    Assignee: NXP B.V.
    Inventors: Olivier Dubreuil, Srdjan Kordic, Theodore Carambeeris