Abstract: A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, an Ethernet communications device includes a physical layer (PHY) unit or a media access control (MAC) unit configured to perform media access control for the Ethernet communications device. The Ethernet communications device includes a security unit configured to manipulate a data stream in a data path within the Ethernet communications device when the data stream violates or conforms to a pre-defined policy.

Abstract: A sense amplifier circuit comprising a first-, second-, third- and fourth-amplification-blocks, each amplification-block comprising: an amplification-block-transistor comprising and an amplification-block-resistor. The amplification-block-transistor includes: a first-conduction-channel-terminal, a second-conduction-channel-terminal that is connected to an amplification-block-output-node, and a control-terminal that is connected to an amplification-block-control-node. The sense amplifier circuit also comprises: an amplification-block-resistor connected in series between an amplification-block-input-node and the first-conduction-channel-terminal; a first-bias-voltage-source connected to the amplification-block-control-nodes of the first- and third-amplification-blocks, a second-bias-voltage-source connected to the amplification-block-control-nodes of the second- and fourth-amplification-blocks.

Abstract: A detection circuit and an integrated circuit. The detection circuit is used for detecting the drift or an open circuit of a first capacitor (C1) on a filtered second power source terminal (220), and the second power source terminal (220) is suitable for acquiring a power source voltage from an unfiltered first power source terminal (210) by means of a first resistor (R1), and is suitable for being coupled to a reference electric potential terminal (230) by means of the first capacitor (C1). The detection circuit comprises a second resistor (R2) and a second capacitor (C2) that are connected in series and coupled between the first power source terminal (210) and the reference electric potential terminal (230), wherein the second resistor (R2) and the second capacitor (C2) have the same time constant as the first resistor (R1) and the first capacitor (C1).

Abstract: Embodiments of an apparatus and method are disclosed. In an embodiment, a method of multi-link communications involves at an access point (AP) multi-link device, allocating Association IDs (AIDs) to non-AP multi-link devices, including allocating one of the AIDs to each of the non-AP multi-link devices, and at the AP multi-link device, generating a first indication element for the AIDs to indicate a buffered data configuration at the AP multi-link device for the non-AP multi-link devices.

Abstract: The disclosure relates to a radar system comprising multiple synchronized transceivers.

Abstract: A duty cycle correction (DCC) circuit for use in relation to differential signal communications, a method of providing duty cycle correction, and communications systems and methods employing same, are disclosed herein. In one example embodiment, the circuit includes a differential signal inverter circuit including first and second inverter circuits, each of which has a respective inverter and respective first and second transistor devices respectively coupled between the respective inverter and first and second voltages, respectively. The circuit also includes a feedback circuit coupled to respective output ports of the respective first and second inverter circuits and also to respective feedback input ports of the respective transistor devices. The feedback circuit operates to provide one or more feedback signals causing one or more of the transistor devices to perform current limiting. Respective duty cycles of output signals respectively are equal or substantially equal based on the current limiting.

Abstract: Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.

Abstract: A network node for coupling to a communication bus, the node comprising: a receiver configured to receive messages from the communication bus; and a transmitter configured to transmit first messages having a first message format and configured to transmit diagnosis messages having a second message format on the communication bus for use in determination of communication errors, wherein said transmitter is configured to send said one or more diagnosis messages having one or more of: (i) a predetermined pattern of symbols; (ii) a predetermined sending schedule; (iii) a predetermined line encoding method; (iv) a predetermined bit rate; (v) a predetermined position in one or more of the first messages; (vi) a predetermined signalling frequency that is out of a frequency band used for transmission of the first messages; and (vii) a predetermined signal strength different from the signal strength used to send the first messages.

Abstract: In connection with an RF communication system, exemplary aspects may involve a method and apparatus for use in a communication system in which a RF receiver may be detecting and processing a first signal in an RF channel. Thereafter, a second received signal may be detected, with the second received signal being assessed, by receiver circuitry, as stronger than the first received signal. In response to the assessment of the second received signal being stronger than the first received signal, the RF receiver circuitry may adjust the gain or signal amplification circuitry for continuing to process the second, stronger, received signal in place of the first, weaker, received signal.

Abstract: In an embodiment, a System-on-Chip (SoC) may include: a plurality of core domains, and a memory coupled to the plurality of core domains through a hardware firewall, wherein the hardware firewall is configured to enforce an adaptive Deny-By-Default (DBD) access policy in response to an event. In another embodiment, a circuit, may include: an access control policy generator configured to produce an adaptive DBD policy, and a hardware firewall coupled to the access control policy generator, the hardware firewall configured to enforce the adaptive DBD policy. In yet another embodiment, a method may include: storing an indication of a first DBD configuration state, the first DBD configuration state usable to enforce a first DBD access control policy, and changing the stored indication to a second DBD configuration state, the second DBD configuration state usable to enforce a second DBD access control policy.

Abstract: A vehicle radar system, apparatus and method use a radar control processing unit generate compressed radar data signals, to apply the compressed radar data signals in parallel as a three-dimensional matrix to a coherent integrator (which generates a two-dimensional matrix of coherently integrated image data) and a non-coherent integrator (which generates a two-dimensional matrix of non-coherently integrated image data), and to generate a constant false alarm rate (CFAR) threshold from the two-dimensional matrix of non-coherently integrated image data for application to the two-dimensional matrix of coherently integrated image data to detect one or more targets in the MIMO radar signal returns from sample values from the two-dimensional matrix of coherently integrated image data that exceed the CFAR threshold.

Abstract: A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal to produce a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is down-converted to an intermediate frequency signal and converted by a high-speed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.

Abstract: A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.

Abstract: A system on a chip allows external NorFlash memory sharing by multiple master devices. The system on a chip is configured to use an external NorFlash memory and includes a plurality of master devices and NorFlash virtualising circuity. The NorFlash virtualizing circuitry is configured to suspend a program operation or an erase operation being carried out on the external NorFlash memory, permit a read operation to be carried out on the NorFlash memory and then resume the suspended program operation or erase operation. Each master device of the plurality of master devices operates as a master to independently access the external NorFlash memory.

Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver, wherein the transceiver is configured to determine bit timings from a data frame received by the receiver. The transceiver is further configured to detect attempts to introduce a signal glitch in a predetermined portion of the data frame and upon detection of the signal glitch, the transceiver is configured to invalidate the data frame on a transmission line and/or disable the transmitter for a predetermined period.

Abstract: A method of processing received Packet Data Convergence Protocol (PDCP) data packets in a PDCP layer module of a telecommunications base station, includes receiving by the PDCP layer module a plurality of data packets, determining by an analysis module of the PDCP layer module a proportion of the data packets received out of sequence over a predetermined number of received data packets, setting an expiry time of a reordering timer of a buffering and reordering module of the PDCP layer module according to the proportion, and starting the reordering timer upon receiving an out of sequence data packet in which the out of sequence data packet is added to a reordering buffer of the buffering and reordering module. If the reordering timer reaches the expiry time, data packets are removed from the reordering buffer and transferred from the PDCP layer module to another layer module of the base station.

Abstract: A mechanism is provided by which a radar image can be generated using mmWave transmissions from 5G-NR type base station antenna arrays. Base stations in 5G-NR use a beam searching sequence utilizing a defined synchronization signal burst (SSB) during their communication initialization with client devices. Embodiments utilize these SSB signals as a radar “chirp” to build a radar image of the base station surrounding in parallel with the typical 5G-NR communication initialization. Antennas on the base station can receive the reflected signals to define the radar image, in conjunction with correlation and time-management logic to properly associate received reflected signals with original transmitted signals. Such information can be processed by a synthetic aperture radar processing logic to form the radar image.

Abstract: A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes etching a gate stack comprising a first nitride layer. The first nitride layer is on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack is oxidized to form a polysilicon layer from the silicon layer, and to form a second oxide layer on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer is formed conformingly covering the second oxide layer. A nitride etch-stop layer is formed conformingly covering the second nitride layer.

Abstract: Described are method and systems that implement time frequency domain threshold interference and localization fusion to resolve interference issues in an automotive radar system, that produces spectrograms using Short-Time Fourier Transform (STFT) for all receiving antennas of the automotive radar system. For each STFT frequency a suppression threshold is determined. Interference is isolated for each STFT frequency by removing the interference from samples that are above the suppression threshold by using a filter. Direction of Arrival (DoA) is estimated for each interference spectrogram cell using measurements from all the receiving antennas. Interference samples are clustered using the DoA into epochs of chirps.