Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.

Abstract: A processor including a pointer storage that stores pointer descriptors each including addressing information, an arithmetic logic unit (ALU) configured to execute an instruction which includes operand indexes each identifying a corresponding pointer descriptor, multiple address generation units (AGUs), each configured to translate addressing information from a corresponding pointer descriptors into memory addresses for accessing corresponding operands stored in a memory, and a smart cache. The smart cache includes a cache storage, and uses the memory addresses from the AGUs to retrieve and store operands from the memory into the cache storage, and to provide the stored operands to the ALU when executing the instruction. The smart cache replaces a register file used by a conventional processor for retrieving and storing operand information. The pointer operands include post-update capability that reduces instruction fetches. Wasted memory cycles associated with cache speculation are avoided.

Abstract: One example discloses a multi-radio device, including: a controller configured to be coupled to a radio; wherein the controller is configured to receive a request to communicate a signal with an initial communication priority from the radio; wherein the controller includes a priority offset module configured to, adjust the initial communication priority by a first offset; and wherein the controller includes a priority escalator module configured to, adjust the initial communication priority by a second offset.

Abstract: Various embodiments relate to a current loop controller configured to control a boost converter, including: an amplifier configured to scale a measured current; a subtractor configured to subtract the scaled measured current from a desired current and to output an error signal; a controller including an integral part and a proportional part configured to produce a control signal based upon the difference signal and a gain value, wherein the gain value is based upon a measured value tps, wherein tps is the on-time plus the secondary time of the boost converter; and a switch signal generator configured to produce a gate signal based upon the control signal, wherein the gate signal controls the boost converter.

Abstract: A defrosting system includes an RF signal source, an electrode proximate to a cavity within which a load to be defrosted is positioned, and a transmission path between the RF signal source and the electrode. The system also includes power detection circuitry coupled to the transmission path and configured repeatedly to take forward and reflected RF power measurements along the transmission path. A system controller repeatedly determines, based on the forward and reflected RF power measurements, a calculated rate of change, and repeatedly compares the calculated rate of change to a threshold rate of change. When the calculated rate of change compares favorably with the threshold rate of change, the RF signal source continues to provide the RF signal to the electrode until a determination is made that the defrosting operation is completed, at which time the RF signal source ceases to provide the RF signal to the electrode.

Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.

Abstract: Various embodiments relate to a protection circuit, comprising: a pad configured to input an external voltage from a connector; a first circuit branch connected to the pad and configured to receive a fast ramp-up over voltage at the pad; a second circuit branch connected to the pad and configured to receive a ramp-up over voltage at the pad; a third circuit branch connected to the pad and configured to output an over voltage detection signal when an over voltage is received at the pad, wherein the third circuit branch includes a voltage divider with a variable resistor with a variable voltage node and an enable switch; and a logic circuit including an enabling transistor configured to control the variable resistor and the enable switch.

Abstract: Various embodiments relate to a current loop controller configured to control a boost converter, including: an amplifier configured to scale a measured current; a subtractor configured to subtract the scaled measured current from a desired current and to output an error signal; a controller including an integral part and a proportional part configured to produce a control signal based upon the error signal; a measuring circuit configured to measure the actual switching period of the boost converter; and a switch signal generator configured to produce a switching signal based upon the control signal and the measured actual switching period, wherein the switch signal controls the boost converter.

Abstract: UAV airways system generally are disclosed. Such UAV airway systems may comprise UAV cargo transportation systems and UAV surveillance and monitoring systems. Such systems preferably overlay and are commensurate with a system of high-voltage power transmission lines of high-voltage transmission system, and electric field actuated (EFA) generators preferably are utilized in UAVs that travel along the transmission lines, in UAV charging stations located along the transmission lines, or in both. Each EFA generator represents a power supply and comprises first and second electrodes separated and electrically insulated from each other for enabling a differential in voltage at the first and second electrodes resulting from a differential in electric field strength experienced by the first and second electrodes arising from the power transmission lines of the high-voltage transmission system.

Abstract: A low power temperature detection method, system, and apparatus sense when a temperature threshold is reached by connecting a current conveyor (111) with a startup bias circuit (112) having a first FET (P1) (connected to level shift a reference voltage to provide an input voltage VS1), a first diode-connected BJT (Q0) (connected to generate a base-emitter voltage based on the junction temperature), and a second FET (P2) (connected to level shift the base-emitter voltage), where the startup bias circuit (112) selectively connects the current conveyor (111) to ground to form a closed loop that is activated only when an emitter current at the first diode-connected BJT (Q0) enters a self-turned-on operation region, thereby activating the current conveyor to detect a temperature threshold being reached by the device junction temperature.

Abstract: A burst-mode controller for a DC-DC converter includes an output module configured to provide a switch control signal to the DC-DC converter. The switch control signal includes a plurality of burst windows, each burst window corresponding to a period of a fixed-frequency burst clock and having a number of switching cycles. The burst-mode controller includes an on-time-control-module configured to receive a compensation signal based on the output voltage of the DC-DC converter, and set an on-time of the switching cycles of the switch control signal based on the compensation signal. The burst-mode controller also includes a burst-control-module configured to regulate the on-time of the switching cycles of the switch control signal by setting the number of switching cycles for each burst window of the switch control signal.

Abstract: A device includes an antenna configured to be disposed within a cavity of an appliance. The appliance includes an electrode and the antenna includes a sheet of conductive material having a surface area that is equal to or greater than a surface area of the electrode. The device includes a voltage sensor coupled to the antenna, an output device, and a controller coupled to the voltage sensor and the output device. The controller is configured to generate an output at the output device. The output is determined by a voltage of the antenna.

Abstract: A device includes a semiconductor die including a transistor. The transistor includes a plurality of parallel transistor elements. Each transistor element includes a drain region, a source region, and a gate region. The semiconductor die includes a first temperature sensor between a first transistor element in the plurality of transistor elements and a second transistor element in the plurality of transistor elements. The first temperature sensor is configured to generate a first output signal having a magnitude that is proportional to a temperature of the first temperature sensor.

Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.

Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

Abstract: Apparatus and methods of providing digital varying output, such as sinusoidal, pulse width modulation, SPWM, control for an inverter comprising at least a first switch and a second switch are disclosed. The method comprising: generating a first binary control signal at a system modulation frequency; generating a second binary control signal at an M-times higher carrier frequency; wherein generating the second binary control signal comprises: providing a periodic counter having a K-times higher reset frequency; calculating M switch-off moments; determining for each, a corresponding switch-off counter value and a corresponding counter sequence value; storing each switch-off counter value in a respective memory location corresponding to the respective counter sequence and dummy values in the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register.

Abstract: A method for estimating a time-of-arrival of a packet received by a receiver includes storing a reference bit-pattern and receiving a plurality of samples in a samples-buffer. In a bit-pattern detector, a matching group of samples having a bit-pattern which matches the reference bit-pattern is identified. In a correlator, a group of three correlation values is determined from the matching group of samples, including a local maximum correlation value, P0, an immediately preceding correlation value, Pm, and an immediately succeeding correlation value Pp. In an estimation unit, a polynomial function f(?) of the difference, ?, between Pm and Pp is used to estimate a timing offset Tfrac, between the local maximum correlation value and a correlation peak. The time-of-arrival is estimated from a time of the local maximum correlation value P0, and Tfrac.

Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

Abstract: A bandgap reference correction circuit comprising a bandgap reference circuit comprising a first resistor; a first oscillator comprising a second resistor, wherein a frequency of a first oscillator output signal of the first oscillator depends on a resistance of the second resistor; and a compensation module configured to: receive the first oscillator output signal from the first oscillator and a reference frequency signal from a reference oscillator; determine the frequency of the first oscillator output signal using the reference frequency signal; and set a resistance of the first resistor based on the frequency of the first oscillator output signal.