Abstract: The invention provides a processing system, comprising a video signal processing unit for processing a video signal, the video signal processing entailing a video signal processing delay, and video delay control for controlling said video signal processing unit in dependence on a maximum allowed value for the video signal processing delay. The invention also provides an audio-video signal source, comprising an output for sending a video signal to a video signal processing unit, and an output for communicating to the video signal processing unit a maximum allowed value for a video signal processing delay entailed by video signal processing in the video signal processing unit.

Abstract: The present invention relates to a video decoder (DEC) for decoding a bit stream (BS) corresponding to pictures (P) of a video signal, the coded pictures being likely to include macroblocks coded in a progressive and in an interlaced way. The decoder includes a decoding unit (DEU) for decoding macroblocks coded in a progressive way, and a hybrid reference construction unit (HRCU) for constructing, for each reference picture, a hybrid reference texture (HRT) which has the property of representing said reference picture in a frame-based and in a field-based manner. Said hybrid reference texture is used by said decoding unit for decoding interlaced macroblocks.

Abstract: The invention relates in general to a method for determining cable termination resistances in communication networks and a corresponding communication network, and is applicable especially to high-speed communication networks in automobiles, which uses dual-wire harnesses like FlexRay e.g.

Abstract: An electronic device with an amplifier output stage (OS) and an over-current detection means (OCDM) for detecting an output over-current (IHS, ILS) of the output stage (OS) is provided. The over-current detection means (OCDM) comprises a level detection means (LDM) for detecting a level of the output current (10) exceeding a first level of the output current (IDET), and a timing detection means (TDM) for detecting a duration during which the output current (10) exceeds the first current level (IDET) being a maximum current level.

Abstract: The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding circuit comprising comparison circuitries for comparing the 4-level input data signal with a clock signal and a one-bit data signal. In dependence upon the comparison results signals are provided to a decode logic circuit, which are indicative of a data bit value of the 4-level input data signal representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal. In dependence upon the signals the decode logic circuit generates then a 2-bit output data signal. The 4-level logic decoder is easily implemented using simple circuit of logic components, which allow modeling using an HDL.

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: In the case of an electronic communication system (100) having; a) at least one base station (10) having at least one antenna unit (16: 16a, 16b), in particular in coil form, which base station (10) is arranged in particular on or in an object to be secured against unauthorized use and/or against unauthorized access, such as on or in, say, a means of transport or on or in an access system, and, b) at least one transponder station (40), in particular in data-carrier form, having at least one antenna unit (44: 44a, 44b), in particular in coil form, which transponder station (40), c) may in particular be carried with him by an authorized user and/or, d) is designed to exchange data signals (22, 24) with the base station (10), in which case, by means of the data signals (22, 24), e) the authorization for use and/or access can be determined and/or, f) the base station (10) can be controlled accordingly, and in the case of a method of detecting and/or guarding against at least one, in particular external, attack, a

Abstract: A device (D1) for transmitting data to a further device (D2) is arranged for transmitting a first class of data (GT) as a guaranteed stream of data-units, and for transmitting a second class of data-units (BE) on a best effort basis. The device (D1) starts the transmission of a burst of data-units which belong to the second class (BE) at a point in time (t2_start) where the remaining time interval (t1_start) until the start of the next burst of first-class data (GT) minus the required time (t2_burst) for transmitting the burst of second-class of data is less than a predetermined time (Tp).

Abstract: An integrated circuit (10) comprises a mixer circuit (14, 54a) and a local oscillator circuit (18, 58). During testing a frequency divider circuit (32, 60) in the integrated circuit (10) divides a local oscillator signal to a frequency below a normal operating range of the local oscillator (18, 58). The integrated circuit applies the divided local oscillator signal to the mixer circuit (14, 54a) instead of the local oscillator signal during testing. Signal properties of a signal derived from the mixer circuit (14, 54a) are measured while the divided local oscillator signal is applied to the mixer circuit (14, 54a).

Abstract: The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22).

Abstract: Systems (1) comprising generating devices (2) comprising sensors (21) for generating sensor signals representing orientations of the generating devices (2) are provided with comparing devices (3) comprising comparators (31) for comparing the sensor signals with reference signals for interpreting the orientations, to increase the number of possible applications. The generating devices (2) and the comparing devices (3) may form parts of one apparatus (4) or of different apparatuses and then communicate wiredly or wirelessly via radio or infrared. Reference sensors (33,52) for generating the reference signals and/or reference memories (34,53) for storing the reference signals may be located in the comparing devices (3) and/or in sources (5) and then communicate wiredly or wirelessly via radio or infrared. Further comparators (36) in the comparing devices (3) may introduce adjustable sensitivities.

Abstract: An instruction issue method for use in a pipelined processor, comprising the steps of: decoding an instruction to be processed to get a type of the instruction; computing the number of cycles to be occupied at execution stage for the instruction, according to the type of the instruction; marking a target operand of the instruction as acquirable in a predefined cycle before the instruction enters write-back stage, according to the number of cycles, so that subsequent instructions taking the target operand as their source operands perform subsequent operations according to the case that the target operand is acquirable.

Abstract: A sensor circuit array (101) comprises a receiver antenna (103) designed to receive electromagnetic radiation, and comprises a sensor element (104) designed to sense at least one parameter in an environment of the sensor circuit array (101). The receiver antenna (103) is connected to the sensor element (104) in such a manner that, upon receiving an activation signal by the receiver antenna (103), the sensor element (104) is activated based on the activation signal so that the sensor element (104) is caused to sense the at least one parameter in the environment of the sensor circuit array (101).

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: A method for detecting a delimiter pattern (SOF) in a signal stream containing a carrier or subcarrier modulated by the delimiter pattern comprises: specifying an expected delimiter occurrence time (t1) of an occurrence of the delimiter pattern and a tolerance zone (tz) within which the expected delimiter occurrence time (t1) may jitter; approximating, within the tolerance zone (tz), a zero of a cross correlation function (CCF) of the data stream with the delimiter pattern, or detecting the phase (?) of the carrier or subcarrier in respect to an arbitrarily defined reference position within the tolerance zone (tz), e.g.

Abstract: A transponder (400) comprising an antenna (401) and an antenna voltage limiter circuit (404) adapted to limit an antenna voltage to a first voltage limit (VPEAK1) when the transponder (400) is in a first operation mode (504) and to a second voltage limit (VPEAK2) when the transponder (400) is in a second operation mode (505), wherein the first operation mode (504) is a mode in which the transponder (400) receives data, and the second operation mode (505) is a mode in which the transponder (400) sends data.

Abstract: An integrated circuit (1a) for a transponder (1), wherein said integrated circuit (1a) is switchable between a TTF (transponder talks first) and an RTF (reader talks first)-mode within a switching timeframe (TF2), wherein the position of the switching timeframe (TF2) is shif table in relation to a timeframe (TF1) allocated to the TTF-mode. In a preferred embodiment, the switching timeframe (TF2) is before a timeframe (TF1) allocated to the TTF-mode by default. After initialization of the transponder (1), the switching timeframe (TF2) is switched to a position after the timeframe.

Abstract: A mobile communication device (1, 10) comprises shielding components that provide electromagnetic shielding or attenuation between a first area (A) and a second area (B, B1, B2) within and/or external of the communication device (1, 10). In said first area (A) an antenna (4) and at least one ferrite (6) are arranged, which ferrite (6) is provided to interact with said antenna (4) and to guide a magnetic flux between said first area (A) and said second area (B, B1, B2).

Abstract: The present invention relates to a video decoder (DEC) for decoding a bit stream (BS) corresponding to pictures (P) of a video signal, the coded pictures being likely to include macroblocks coded in a progressive and in an interlaced way. This decoder comprises a decoding unit (DEU) for decoding macroblocks coded in a progressive way and, according to the invention, a multiple instance unit (MIU) for presenting, for each field-predicted macroblock, a motion compensation vector associated with each field, constructing as many predicted entire macroblocks as fields with each corresponding motion compensation vector, and reconstructing said field-predicted macroblock by re-interlacing fields respectively taken from each corresponding predicted entire macroblock.

Abstract: A membrane (2) for an electroacoustic transducer (1) is disclosed, wherein a thickness (d) of said membrane (2) and an average Young's modulus (Eavg) of said membrane (2) are chosen in such a way that the critical load (Fbc), which causes the membrane (2) to buckle and/or crinkle, is increased compared to a reference membrane. The reference membrane made of Polycarbonate has the same shape, dimension, and stiffness in its direction of movement (MOV) as said membrane (2). According to the result of investigations on buckling and/or crinkling, said effect occurs with different critical buckling/crinkling loads for membranes of the same shape and dimension, but made of different materials, even when the stiffness of the membranes in their direction of movement—and hence their resonant frequency—is identical.