Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable updating of slave device output banks sequentially or simultaneously. The communications system includes two or more slave devices and/or a slave device having two or more banks of output drivers. Each slave device receives serial data and provides a data word assembled from the serial data. A programmable register in each slave device is programmed, using the communications protocol, to select one or more slave device configurations. Each of the two or more slave devices and/or two or more banks of output drivers updates either sequentially, or in coordination with other of the two or more slave devices and/or two or more banks of output drivers, based on each slave devices configuration selected by its programmable register.

Abstract: An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S1) having a core with input and/or output pins and at least one power supply connection pad (PP) and one ground connection pad (GP) connected to a chosen one of the input and/or output pins and respectively connected to power supply and ground connection zones (MZ1) of a printed circuit board (PCB), and a passive integration substrate (S2) set on top of the digital and/or analog integrated circuit (S1) and comprising i) at least first and second input zones respectively connected to the ground (GP) and power supply (PP) connection pads to, be fed with input ground and supply voltages, ii) input and/or output zones connected to chosen core input and/or output pins, and Ëi) a passive integrated circuit (PIC) connected to the first and second input zones and arranged to feed the substrate input and/or output zones with chosen ground and supply voltages defined from the input ground and supply voltages.

Abstract: In an arrangement comprising a magnetic field sensor which is effectively connected to a magnetic encoder which is arranged such that it can move with respect to the sensor and comprises magnetic poles with alternating polarity, wherein the sensor consists of at least two half-bridges which are in each case formed by two magnetoelectric elements, the electrical properties of which depend on the magnetic field strength, it is provided that the elements of each half-bridge have resistance/field strength characteristics which run in opposite directions and are arranged such that they are in phase with respect to the magnetic field, and that the spacing between the half-bridges corresponds to part of the pole pitch of the magnetic encoder.

Abstract: The invention is related to a device (DEV) for applying operating data (OPDAT) of said device (DEV) and/or data associated (ASDAT) with playback data (PLDAT) played by said device (DEV) to a remote device (RD). The device (DEV) comprises a memory (MEM) and a power supply (POW, BAT) arranged to power said device (DEV) and said memory (MEM). Operating data (OPDAT) and/or said associated data (ASDAT) are stored in said memory (MEM) during operation of said device (DEV). Subsequently said data (OPDAT, ASDAT) can be read by means of said remote device (RD) being in the proximity of device (DEV). According to the invention said memory (MEM) is designed to be powered by means of radio waves emitted by the remote device (RD). Hence data (OPDAT, ASDAT) can even be read if the power supply (POW, BAT) is not available, because it is switched off or broken for example .

Abstract: The invention provides a method for ensuring a secure NFC functionality of a wireless mobile communication device comprising the steps of detecting the charge state of a first energy source (1) which supplies the voltage for operating the wireless mobile communication device (S1); switching off the first energy source and switching on a second energy source (2), if the detected charge state of the first energy source (1) falls below a threshold (S2); detecting the charge state of the second energy source (2), if an external NFC signal is received (S3); charging of the second energy source via voltage induced by a received NFC signal to allow at least one secure NFC transaction, if the detected charge state of the second energy source (2) is below a threshold (S4). Furthermore the invention provides a wireless mobile communication device having a secure NFC functionality, which is always ready for operation of at least the secure NFC functionality.

Abstract: The rate at which a receiving device processes a stream of data packets received from an asynchronous device is synchronized with the rate at which the asynchronous device is transmitting the data packets. The device stores the received data packets in a buffer “memory and processes the data from the buffer memory at a sampling rate determined by a sampling rate controller. The sampling rate is adjusted based on a threshold comparison of a memory fill level pointer to synchronize the rate at which the data is processed with the rate at witch the data is being received from the asynchronous device. By synchronizing the rates, buffer underflow and overflow conditions may be avoided.

Abstract: An integrated circuit with a test interface contains a boundary scan chain with cells (14) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell (14) is also coupled between a respective one of the terminals (16) and the core circuit (10). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells (14) transport data serially along the boundary scan chain while selectable second ones of the cells (14) write or read data that has been or will be transported through the first ones of the cells (14) in the further mode to or from the terminals (16) from or to the scan chain.

Abstract: A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.

Abstract: The invention relates to a trench MOSFET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region (10) 10 and a gate electrode (32) next to the body (12).

Abstract: Usually, power supplies are not capable of switching off part of the outputs of a main power supply during stand-by. Due to this, stand-by power supplies are used in addition to operation power supplies. Consistent with an example embodiment, a forward converter is provided, including switches in the rectifier circuit thereof. Due to this, the rectifier circuits may be selectively switched on and off. Advantageously, this may allow that the main outputs of such a forward converter are switched off while on stand-by.

Abstract: An amplifier circuit (100) includes a driver stage (120) with active devices (140) for pre-amplification and output of a pre-amplified signal; and an output stage (160) with active devices (180) for further amplification of the pre-amplified signal and output of an amplified signal. A detector (190) measures levels of forward and reflected parts of the amplified signal, and a control circuit (145) independently and selectively controls turning on and off of the active devices (140, 180) of the driver and output stages (120, 160) as a function of the levels of the forward and reflected signals to substantially maintain linearity of the amplifier circuit (100) with load variations.

Abstract: A device (100) for processing audio data (101), wherein the device (100) comprises a mid-frequency filter unit (105) adapted to selectively filter a mid-frequency range component of the audio data (101) in such a manner that amplitudes of different frequency sub components of the mid-frequency range component of the audio data (101) are scaled so that the scaled amplitudes reflect relations between the original amplitudes of the different frequency sub-components.

Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

Abstract: Continuous-time filter system with self-calibration means. The system comprises a master control unit (36) and a slave unit with one or more slave filters (27.1-27.n). The master control unit (36) comprises an integrator (30) having circuit elements (33, C) which match those elements of the slave filter (27.1-27.n) that define the slave filter's time constant (?). Furthermore, the master control unit (36) comprises a voltage comparator (35) connected to an output (34) of the integrator (30), the voltage comparator (35) providing an output frequency signal (fcom), and a phase frequency comparator (PFC; 28) providing a control signal (?) as output signal, the phase frequency comparator (PFC; 28) receiving said output frequency signal (fcom) and a reference frequency signal (fref) as input signals. The slave unit comprises said at least one slave filter (27.1-27.n), the slave filter (27.1-27.

Abstract: Present invention relates to an oscillator circuit comprising: resonator means (102) and, first and second emitter followers (116, 118) being symmetrically coupled to the resonator means and been connected to further emitter followers (120, 122) for providing capacitive loading.

Abstract: There is provided a switch mode power supply circuit including at least one inductive component coupled to an associated switching device for cyclically connecting the inductive component to a source of power. The circuit includes a signal output representative of a voltage at a junction of the at least one inductive component to the switching device. The circuit further comprises a hard switching amplitude detector for deriving a measure of hard switching amplitude occurring in operation in the switching device the detector including a signal processing path for receiving the signal output and generating the measure of hard switching amplitude therefrom. The signal path includes: a signal differentiator for imperfectly differentiating the signal output to generate a corresponding imperfectly differentiated signal; and a signal integrator for integrating the imperfectly differentiated signal in a temporally-gated manner for generating the measure of hard switching.

Abstract: A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor. The invention also relates to a display device and an arrangement for controlling a display device, which each comprise a non-volatile semiconductor memory.

Abstract: A method for the self-testing of a reference voltage in electronic components includes a circuit arrangement for a self-test of the reference voltage that can be implemented in the form of an on-chip test, eg., for which no external reference voltage source is required. The reference voltage (Uref) is fed to a voltage-controlled oscillator whose output forms the input to a Wien-Robinson bridge whose output signal is checked in a phase detector for its phase shift relative to the input to the Wien-Robinson bridge to check the balance of the Wien-Robinson bridge. The Wien-Robinson bridge is set to be balanced at a frequency (OMEGAref.test) that is generated in the oscillator at the nominal value(Uref.tes) selected for the reference voltage (Uref), and a pass signal is generated if the bridge is balanced and a fail signal is generated if it is not.

Abstract: A multiplier apparatus is arranged for multiplying a first long integer entity with a second long integer entity modulo a prime number. In particular, the comprises a pipelined multiplier core, whilst executing the overall multiplication in Montgomery fashion.

Abstract: An apparatus and method is provided for protecting data in a non-volatile memory by using an encryption and decryption that encrypts and decrypts the address and the data stored in the non-volatile memory using a code read only memory that stores encryption and decryption keys that are addressed by a related central processing unit at the same time data is being written or read from the non-volatile memory by the central processing unit.