Abstract: In a method to improve error reduction in a digital-to-analog converter (DAC), comprising a mapping matrix block and a plurality of selectable source units which supply signals that in combination provide for analog output signals, mapping input signals, obtained from digital input signals to be converted into the analog output signals, are supplied to the mapping matrix block. In the mapping matrix block mapping output signals are generated in response to said mapping input signals and to mapping control signals derived from errors occurring in the plurality of selectable source units. At least one of the mapping input signals is applied for the substantially simultaneous generation of the mapping output signals for a number of source units.

Abstract: An optical receiver circuit comprising an optical converter circuit (38), comprising a photodiode and converting optical power into electrical power, a sensor circuit for deriving a control voltage VCONTR as a characteristic value of the electrical power output by the optical converter circuit (38); and an attenuator circuit (44) having a variable attenuation, the attenuation being controlled by the characteristic value of the electrical power output by the sensor circuit so as to obtain a constant output signal level of the optical receiver circuit. An output circuit is also provided and comprises a matching network (46), an amplifier stage (48) and an output transformer (50).

Abstract: Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.

Abstract: A trench-gate transistor (1) has an integral first layer of silicon dioxide (31) which extends from the upper surface (10a) of the semiconductor body (10) over top corners of each cell array trench (20), the integral first layer also providing a thin gate dielectric insulating layer (31A) for a thick gate electrode (41) and the integral first layer also providing a first part (31B) of a stack of materials which constitute a thick trench sidewall insulating layer (31B,32,33) for a thin field plate (42), a layer of silicon nitride (32) providing a second part of the stack and a second layer of silicon dioxide (33) providing a third part of the stack. The integrity of the first silicon dioxide layer (31) over the trench (20) top corners helps to avoid gate (41) source (24) short circuits. In a method of manufacture (FIGS.

Abstract: A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the parallel memory element for the storage of the data signals.

Abstract: A decoupling module for decoupling high-frequency signals from a voltage supply line, the module including a plurality of parallel-connected capacitors (K1, K2, . . . ), which each have a capacitance (C1, C2, . . . ), and are characterized in that at least one of the capacitors (K1) has an inductance (L1) which is selected dependent on the capacitance (C1) of the capacitor (K1) and the voltage supply line inductance (L12), so that a resonance is generated which compensates the self-resonance of the system from at least a further capacitor (K2, . . . ) and the entire voltage supply line (S). L12 is the inductance of the voltage supply line running between the parallel-connected capacitors.

Abstract: A power converter comprises an inductor (LP) and a controllable switch (CF) coupled to the inductor. A switch controller (1) supplies a periodic switching signal (VC1) which has a repetition time and a duty cycle to the controllable switch (CF) to generate a periodical inductor current (IL) through the inductor. A generator (2) generates an emulated signal (IE) based on timing information (TI) which represents the repetition time and the duty cycle to emulate a current signal being representative of the inductor current. A comparator (3) compares the emulated signal (IE) with the current signal (CS) to obtain an error signal (E). A generator controller (4) receives the error signal (E) to supply a control signal (VD) to the generator (2) to adapt a property of the emulated signal (IE) to become substantially equal to a property of the current signal (CS).

Abstract: Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types of faults is proposed, in which two cells of two logically adjacent rows or columns are written with complementary logic data. If a read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect is demonstrated.

Abstract: A method of canceling a narrow-band interference signal in a receiver is provided. A reference signal (ref_in) is subtracted from a received input signal (in). the phase of a result of the subtraction is calculated on the basis of an arctangent function. An unwrap function on the output signal from the arctangent function is performed by removing the modulo 2? limitation introduced with the arctangent function, in order to produce an absolute phase representation. A frequency offset is determined by comparing phase representation values which are shifted predetermined in time. The narrow-band interference signal is canceled based on the result of the determined frequency offset.

Abstract: A transmitter comprises a power amplifier (PA) which has an amplifier powersupply input (PI) and an output (PAO) to supply a transmission signal (Vo) with an output power (Po). A power supply (PS) has power supply outputs (PSO1, PSO2) to supply a first power supply voltage (PV1) and a second power supply voltage (PV2). A switching circuit(SC) is arranged between the power supply outputs (PSO 1, PSO2) and the amplifier powersupply input (PI).

Abstract: A device includes a main power source for supplying power, and a memory for storing an augmented time which is greater than a current time and is updated periodically using a first clock. An auxiliary power source supplies power to a second clock for providing the current time when the main power source is incapable of providing power. A controller powered by the auxiliary power source is configured to set a start time when main power source is incapable of providing power. The auxiliary power source does not supply power to the second clock.

Abstract: A system for wireless communication, particularly for receiving communication signals, said system comprising: A main antenna structure (330), said antenna structure adapted to receive a communication signal (325a) as a first internal signal; and an antenna cable, said antenna cable having a first end operationally coupled to said main antenna structure and a second end, said antenna cable including a main conductor (335) for passing said first internal signal, and a second receiving conductor (340), said second receiving conductor adapted to receive said communication signal as a second internal signal, and wherein said second receiving conductor as a receiving element is spatially separated from the main antenna structure. The disclosed antenna system and apparatus for the extraction of the second, spatially-separated received signal achieves spatial diversity to alleviate multipath effects in wireless communication systems.

Abstract: When a reference signal is generated for a digital-to-analog converter in the feedback path of a sigma-delta modulator, the reference signal can contain modulated error signals, for example when the reference generator implements dynamic element matching. By controlling the reference signal generation in dependence on the bitstream output from the sigma-delta modulator, the effects of intermodulation of the reference signal with the bitstream can be reduced.

Abstract: A data processing system is provided comprising at least one processing unit (10) for processing data; a memory means (40) for storing data; and a cache memory means (20) for caching data stored in the memory means (40). Said cache memory means (20) is associated to at least one processing unit (10). An interconnect means (30) is provided for connecting the memory means (40) and the cache memory means (20). The cache memory means (20) is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means (30) as introduced by a data transfer (DO-Dm) between the memory means (40) and the cache memory means (20).

Abstract: Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line (110) and a clock line (120) used to implement a communications protocol. The communications system includes a slave device having address pins (400), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (410), detects a second state of the address pins (420) subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address (430) as a functional relationship between the first state and the second state of the address pins.

Abstract: The electronic device (100) of the invention comprises a semiconductor device (30) and a low-pass filter (20), which are present in a stacked configuration, and which together include a phase locked loop. The low-pass filter is preferably embodied by vertical trench capacitors, and preferably comprises a drift compensation part. The device (100) can be suitably provided in an open loop architecture. In a preferred embodiment, the low-pass filter comprises a large capacitor (C2) and a small capacitor (C1) connected in parallel, the large capacitor (C2) being connected in series with a resistor (R1).

Abstract: The invention relates to a method of packaging or a device for packaging an electronic component, such as semiconductor device, whereby the component is positioned in a cavity of a foil by tweezers and is supported by means of a further foil which is attached to the foil at one side thereof. According to an example embodiment, the component is first placed into the cavity of the foil by the tweezers, and only after that is the further foil positioned adjacent thereto and attached to the foil. The tweezers are moved through the foil to pick up the component, hold it, and move it into the cavity. A feature of this embodiment is that the component may be temporarily supported, by a supporting means after being positioned in the cavity and before being attached to the further foil, and the foil with the component is moved in a longitudinal direction of the foil.

Abstract: An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c).

Abstract: A bondwire decoupling filter 300 for filtering RF noise from a transceiver bus 330 of a transceiver 303 connected a device 302 to be protected from RF noise. The filter includes an external capacitor 315 adapted to receive an output from a device 302 to be protected from the RF noise; a first pair of bondwires 305, 307 each having respective first and second ends, and the first pair of bondwires is connected to the external capacitor 315 at respective first ends. A first bondwire 307 of the first pair of bondwires 305, 307 is connected to an output of a voltage regulator 302, and a second bondwire 305 of said first pair of bondwires being connected to the transceiver bus 330 at respective second ends. A second pair of bondwires 310, 312 each having respective first and second ends, are connected to a ground at respective first ends, and connected respectively to a voltage regulator 302 and a transceiver bus 330 at respective second ends.

Abstract: An amplifier circuit (100) includes a driver stage ( ) 120 with at least an active device (140) for pre-amplification and output of a pre-amplified signal; and an output stage (160) with at least an active device (180) for further amplification of the pre-amplified signal and output of an amplified signal. A phase shifter (155) shifts the phase of the pre-amplified signal. A detector (190) measures levels of forward and reflected parts of the amplified signal, and a gain and phase control circuit (145) independently and selectively controls and adjusts the phase shifter (155) for optimal amplifier performance and minimal difference between the forward and reflected signals. The gain and phase control circuit also independently and selectively controls and modifies the gain of the active devices (140, 180) of the driver and output stages (120, 160) as a function of the levels of the forward and reflected signals to substantially maintain constant linearity of the amplifier circuit (100) with load variations.