Abstract: A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

Abstract: A simplified de-correlation method in CDMA multi-user detection comprises: a. receive wireless symbols S; b. obtain a channel correlation matrix R, take a part from R to get a partial correlation matrix RP; c. do inversion operation to the partial correlation matrix RP, then obtain matrix V(m); d. recover original data symbols D from received symbols S by V(m) that the location of original data symbols D corresponds to.

Abstract: The invention relates to a receiver (1, 49, 51, 52, 54) for receiving RF signals. The known receiver comprises a phase-locked loop which is controlled by the stereo pilot. Because of unwanted frequency changes, a sampling rate converter precedes the stereo decoder. Filtering operations within a complex range can be performed by means of the invention.

Abstract: The present invention provides a method of lithographic patterning in order to the strength of the patterned photoresist. The method comprises: applying to a surface to be patterned a photoresist (18) comprising a polymer resin, a photocatalyst generator which generates a catalyst on exposure to actinic radiation, and a quencher; and exposing the photoresist (18) to actinic radiation through a mask pattern (12). This is followed, in either order, by carrying out a post-exposure bake; and developing the photoresist (18) with a developer to remove a portion of the photoresist which has been exposed to the actinic radiation. The polymer resin is substantially insoluble in the developer prior to exposure to actinic radiation and rendered soluble in the developer by the action of the catalyst, and wherein the polymer resin is crosslinked by the action of the quencher during the bake.

Abstract: A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).

Abstract: An arrangement for optimizing the frequency response of an electro-acoustic transducer (10), comprising the electro-acoustic transducer (10) and a damping element (12) arranged behind the sound emanating or receiving side of a membrane (14) of the electro-acoustic transducer (10), wherein an air gap (16) is provided between the damping element (12, 13) and the membrane (14), which air gap (16) is sufficiently small for intimately acoustically coupling the membrane (14) with the damping element (12, 13), wherein the damping element (12, 13) is adapted to dampen an air flow created by the membrane (14) when moving.

Abstract: A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterised in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alky

Abstract: In the method for controlling access of a plurality of requestors to a shared memory, the following steps are repeated for successive time-windows: receiving access requests from various requestors (S1), determining a type of access requested by the requests, comparing the requested access type with an access type authorized for a respective time-window according to a back-end schedule, generating a first selection of the incoming requests which have the prescribed access type for the relevant time-window, dynamically selecting one of the requests from the first selection.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semi-conductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2).

Abstract: The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2?m. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.

Abstract: A transmitter has a power amplifier (40) to amplify an input signal having amplitude modulation, a supply voltage controller (10) to control a supply voltage of the power amplifier (40) according to the envelope, a sensor (R1) for sensing a modulation of a current drawn by the power amplifier (40), a delay detector (20) for detecting a delay of the controlled supply voltage relative to the sensed current, and a delay adjuster (30) for compensating the relative delay according to the detected delay. By sensing a current drawn, the delay detected can include any delay contributed by the power amplifier (40) up to that point, and yet avoid the more complex circuitry needed to derive the delay from an output of the power amplifier. Thus the distortion and out of band emissions caused by differential delays can be reduced more effectively.

Abstract: In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9).

Abstract: A processing system includes a processor and a physical memory (500) with a single-size memory port (505) for accessing data in the memory. The processor is arranged to operate on data of at least a first data size and a smaller second data size. The first data size is equal to or smaller than the size of memory port. The processing system including at least one data register (514) of the first data size connected to the memory port (505), and at least one data port (525) of the second data size connected to the data register (525) and the processor for enabling access to data elements of the second size.

Abstract: Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually arranged according to a chessboard pattern. These connections extend in a direct path through vertical interconnects and bumps to bond pads at the integrated circuit, which bond pads are arranged in a corresponding chessboard pattern. As a result, an array of direct paths is provided, wherein the voltage supply connections form as much as possible the coaxial center conductors of a coaxial structure.

Abstract: An oscillator circuit has a first and a second piezoresistive resonator (1,2), each having a resonant frequency, each piezoresistive resonator having an input for driving the resonator, and each piezoresistive resonator having its input coupled directly to an output of the other of the resonators, to provide feedback according to a resistance of the respective resonator without amplification and without a phase shifter. This enables feedback without the need for another component to provide the phase shift. This means a simpler circuit can be used, which can facilitate greater integration and hence lower costs. By using piezoresistive resonators the need for an external crystal can be avoided, enabling greater integration and lower costs.

Abstract: The integrated circuit comprises: —an on-chip access right manager (40) to grant or deny access to a memory segment to a peripheral device (10) according to predetermined access rights upon reception of a read instruction from the peripheral device, —an on-chip lock (50) connected to a memory data bus, the lock being controllable by the access tight manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted.

Abstract: A method for defining a sequence of tests for testing a plurality of electronic devices including integrated circuits is disclosed. A reference group of devices is defined (110), after which the devices in said group are subjected to all available tests under consideration (120). For each test, the test results are collected, from which a fault coverage metric of the test for the group of devices is extracted (130). Next, a test benefit is calculated for each test (140), which is a ratio between the fault coverage metric and the test duration of said test. The test sequence is built by repeatedly adding tests to the sequence on the basis of their test benefits (160) until the overall fault coverage of the test sequence has reached a predefined threshold (170). Consequently, a test sequence that is optimized in terms of test cost is obtained.

Abstract: A method for calculating a timeout parameter in a communication session, comprises the steps of initiating a session; calculating a throughput of the connection during initialisation of the session by measuring a time span between sending and receiving a data packet on a target communication device 101 including a fixed computational time delay of the initiator communication device 102, wherein the packets are smaller than a maximum packet size; calculating a maximum round trip time for the maximum data packet that is possible to be sent and received based on the calculated throughput; and setting a session timeout parameter equal to the calculated maximum round trip time.

Abstract: The invention relates to a method for encoding/decoding a video stream including a plurality of images (A, B, C) in a video processing apparatus having a processing unit (11) coupled to a first memory (12), further comprising a second memory (13), comprising the steps: providing a subset of image data stored in the second memory (13) in the first memory (12), —simultaneous encoding/decoding of more than one image (B, C) of the video stream, by accessing said subset, wherein the simultaneously encoding/decoding is performed by access sharing to at least one image (A).