Abstract: There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes one end of the passage (7). The non-conductive barrier layer (10) is plasma treated to transform an upper portion thereof (10b) into a conductive layer, while a low portion thereof (10a) comprising material that has penetrated pores of the di-electric material remains non-conductive. The passage (7) is then filled with a second copper region (13) forming an electrical interconnect with the first copper region (3) via the now conductive upper portion (1Ob) of the barrier (10). As a person skilled in the art will know, all embodiments of the invention described and claimed in this document may be combined without departing from the scope of the invention.

Abstract: The invention relates to a Method, a Communication System and an Communication Unit for protecting incumbent services whereas in the incumbent services first information is exchanged between first communication means by radio frequency transmission within a first bandwidth using a first protocol and second information is exchanged between second communication means by radio frequency transmission within a second bandwidth using a second protocol and the second bandwidth is overlapping and larger than the first bandwidth. The problem to be solved is to reduce or to eliminate an interference of secondary services to incumbent services.

Abstract: A processing system for executing instructions comprises a first part (11) having address information and a plurality of data bits, Eo to EN. According to one embodiment, each data bit E0 to EN directly selects a corresponding element 130 to 13N forming a second part of the instruction set (for example a VLIW). In this manner, the first part (11) is used to only select elements that do not comprise NOP instructions, thereby avoiding power being consumed unnecessarily. According to an alternative embodiment, different groups of elements in the second part (13) may be selected by a number encoded in the first part (11), using data bits Eo to EN. Preferably, these different groups reflect the most likely used combinations in a program.

Abstract: A micro-electromechanical device has a substrate (60), a movable element (15), a pair of electrodes (40) arranged on the substrate and on the movable element to move the movable element, and a controller (50) to supply the electrodes. To move the movable element to an intermediate position one or more pulses are applied during the movement, timed to compensate for under or over damping of the movement. This can reduce a settling delay. It can be applied to tunable RF capacitors. To control a decrease in the gap, a single pulse of a maximum supply level compensates for the inherent slowness of the device and over damping. To compensate for under damping, the pulses have a period corresponding to a resonant frequency, and comprise peaks and troughs above and below the final supply level, such that successive ones of the peaks and troughs are closer to the given supply level.

Abstract: A shift register circuit is provided for storing instruction data for the testing of an integrated circuit core. The shift register circuit comprises a plurality of stages, each stage comprising a serial input (si) and a serial output (so) and a parallel output (wir_output) comprising one terminal of a parallel output of the shift register circuit. A first shift register storage element (32) is for storing a signal received from the serial input (si) and providing it to the serial output (so) in a scan chain mode of operation. A second parallel register storage element (38) is for storing a signal from the first shift register storage element (32) and providing it to the parallel output (wir_output) in an update mode of operation. The stage further comprises a feedback path (40) for providing an inverted version of the parallel output (wir_output) to the first shift register storage element (32) in a test mode of operation.

Abstract: The present invention relates to a method, for watermarking a processing module (105), said processing module (105) being configured to process an electronic signal thereby forming a processed signal, comprising the steps of applying a first functional operator (104) arranged to cause a significant alternation to said processed signal, said first operator (104) being embedded in said processing module (105), and arranging a second functional operator (109) configured to co-operate with said first operator (104) such that said alternation is essentially cancelled. The second operator (109) is adapted to act as an extractable identifier serving as a watermark for said processing module (105). An advantage with the method is the fact that since the first and the second operators are implemented as functional processing blocks, conventional debugging tools can not be used to attack the processing module.

Abstract: The present invention relates to a video encoder (ENC) for encoding frames (FR) of a video signal before transmission, said video encoder (ENC) including an encoding decision unit (EDU) for deciding which kind of coding will be used for each data of said frame (FR) in an encoding unit (ENU). Said video encoder (ENC) further implements a freshness map calculation unit (FMCU) for calculating, throughout the time, for each data of said frame (FR), a corresponding freshness value (FV) taking into account Intra and Inter prediction mechanisms, independently from a calculation of a distortion. Said freshness value (FV) express on which degree encoded data (ED) are relying on previously transmitted data and said freshness value (FV) is used by said encoding decision unit (EDU).

Abstract: The invention relates to a method for stabilizing a video recording of a scene made by a video camera and represented by video data, said method comprising the steps of subdividing said video data into a plurality of successive frames themselves divided into a plurality of blocks, determining for each block of each frame a motion vector representing the direction and magnitude of the motion in said block, said vector at an instant t being called global motion vector GMV(t) and representing said motion at the instant t with respect to the previous frame, defining a modified vector called integrated motion vector IMV(t) at the instant t and designating the final motion vector correction to be applied to the current frame in view of its motion correction, said integrated motion vector being given by the expression:IMV(t) = GMV(t)+a(E).

Abstract: A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement (20) timed with a first, scan, clock signal (42). The test vector bits are passed between adjacent portions of the shift register arrangement timed with the first clock signal (42) and an output response of the integrated circuit to the test vector is provided and analyzed. The output response of the integrated circuit to the test vector is provided under the control of a second clock signal (56) which is slower than the first clock signal. This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate.

Abstract: A high frequency power device (100) is described comprising a high frequency power transistor (102) having a first main electrode, a second main electrode acting as output electrode and a control electrode, and an output compensation circuit (104) for compensating parasitic output capacitance of the transistor (102). The output compensation circuit is physically positioned relative to the transistor such that a shorter bond wire between the output electrode of the transistor and an output lead of the high frequency power device is obtained. The output compensation circuit (104) therefore is physically located in between an input lead (108) of the high frequency power device (100) and the transistor (102). The inductance introduced by the bond wire Lcomp from the output compensation circuit (104) to the output electrode of the transistor (102) can be used as a feedback signal.

Abstract: The invention relates to a circuit arrangement (12) for providing voltages for generation of different gray levels in a display device (11). It further relates to a display device (11) applying such circuit arrangement (12). The invention further relates to a method for providing different gray level curves (33-36) representing different voltage characteristics supplied to a display device (11). To provide a circuit arrangement (12) and a method which are able to generate a wide range of gray level curves (33-36) a circuit arrangement (12) is proposed including a first voltage unit (21); a second voltage divider unit (22) having a plurality of tap points (x); at least one amplifying unit (24, 25) coupled between the first voltage unit (21) and the second voltage divider unit (21, 22), wherein at least one programmable current source (26, 27, 28, 29) is provided for injecting a current (Imain) into a tap point (x) of the second voltage divider unit (22).

Abstract: A fine OFDM symbol synchronization method comprising the steps of: estimating (in 36) a channel impulse response (CIR) from received predetermined pilots present in OFDM symbols, the pre-determined pilots being arranged within the OFDM symbol at frequency intervals corresponding to n carrier frequencies, and their positions being shifted by k carrier frequencies from one OFDM symbol to the next, so that it is sent on the same frequency earner every m OFDM symbols, and thus m*k=n, m, n and k being integer numbers greater than one, and fine-tuning (in 60) the position of a time-domain-to-frequency-domain window used for receiving OFDM symbols, according to the position of at least one power peak in the estimated channel impulse response, wherein, if there are channel impulse response replicas in the estimated channel impulse response, the positions of correlated power peaks spaced apart by a multiple of Formula (I) is used for finding the position of the at least one power peak used n for fine-tuning, where Tu

Abstract: The invention relates to a method of manufacturing a MEMS capacitor microphone and further to such MEMS capacitor microphone. With the method a MEMS capacitor microphone can be manufactured by stacking pre-processed foils (10) having a conductive layer (11a,11b) on at least one side. After stacking, the foils (10) are sealed, using pressure and heat. Finally the MEMS capacitor microphones are separated from the stack (S). The pre-processing of the foils (preferably done by means of a laser beam) comprises a selection of the following steps: (A) leaving the foil intact, (B) locally removing the conductive layer, (C) removing the conductive layer and partially evaporating the foil (10), and (D) removing both the conductive layer as well as foil (10), thus making holes in the foil (10). In combination with said stacking, it is possible to create cavities and membranes. This opens up the possibility of manufacturing MEMS capacitor microphone.

Abstract: A gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) comprises a reactive signal divider (CLN) followed by an amplifier arrangement (A1, A2 . . . , A7, ACC). The reactive signal divider (CLN) may be in the form of, for example, a capacitive ladder network. The gain-controllable stage (CLN, A1, A2 ..., A7, ACC) has a gain factor that depends on a signal division factor that the reactive signal divider (CLN) provides. The reactive signal divider (CLN) forms part of a filter (LC). The signal division factor is adjusted on the basis of a frequency (F) to which the receiver is tuned and a signal-strength indication (RS).

Abstract: In a controller (CC2) for controlling a synchronous rectification switch (S2), the controller (CC2) comprises a sensing circuit (SRL) for sensing an output (D2) of the synchronous rectification switch (S2) at an end of a blanking time to obtain a sense signal (Q), and a control signal generating circuit (AND1) for generating a control signal (G2) for the synchronous rectification switch (S2) in dependence on the sense signal (Q).

Abstract: The SINR (signal-to-interference+noise ratio) estimator comprises a low-pass filter (66) to filter a variance ?? computed from the received pilot symbol amplitude to obtain an estimated variance ?? with a reduced bias, wherein the low-pass filter has an adjustable coefficient and the estimator comprises an electronic controller able to adjust the value of the adjustable coefficient according to the number of pilot symbols received during a timeslot.

Abstract: In a receiver, a synchronization circuit (MIX2, OSC, C1, R1) provides a set of oscillator signals (OSI, OSQ) that are synchronized with a carrier of an amplitude-modulated signal. The set of oscillator signals (OSI, OSQ) comprises a quadrature oscillator signal (OSQ), which is substantially 90° phase shifted with respect to the carrier of the amplitude-modulated signal. A quadrature mixer (MIX2) mixes the quadrature oscillator signal (OSQ) with the amplitude-modulated signal so as to obtain a quadrature mixer output signal (MO2a). A phase-error corrector (PEC) adjusts the phase of the oscillator signals in response to a variation in the magnitude of an alternating current component (AC) in the quadrature mixer output signal (MO2a).

Abstract: A switchable folding circuit for an analog-to-digital converter is provided. The switchable folding circuit comprises a plurality of circuit stages wherein each of the circuit stages comprises a differential pair, a current source and a switching unit. The differential pair is connected to the current source via the switching unit and the circuit stages are inversely connected to one another.

Abstract: The invention relates to a device that comprises a memory circuit with memory cells that use floating gate storage transistors, which are conventionally called non-volatile memory cells. A particular embodiment relates to a teletext circuit. A teletext processing circuit comprising a decoder logic circuit and a memory circuit integrated together in an integrated circuit, the memory circuit comprising memory cells for storing teletext page data, the memory cells comprising floating gate storage transistors to store the teletext page data. The page data from memory is used to control the content of displayed teletext images.

Abstract: To reduce chip size and lower cost by using a method of multiplexing a device to filter a plurality of signals, the present invention provides an apparatus for filtering the plurality of signals, comprising: a group of storage units, for storing the plurality of signals, wherein the group of storage units comprises a plurality of storage units, each of which is used to store corresponding signal segments in each signal and output the stored signal segments in a predefined order; and a processing module, for weighting and combining the output signals from the group of storage units, to obtain a plurality of filtered signals corresponding to the multiple channels of signals. The group of storage units may further comprise a group of combining units, for combining output signal segments from the storage units to be processed with a same weight value. The present invention further provides the corresponding method for filtering a plurality of signals.