Abstract: To provide a method for the self-testing of a reference voltage in electronic components, by means of which method there is defined a circuit arrangement for a self-test of the reference voltage that can be implemented in the form of an on-chip test, i.e. for which no external reference-voltage source is required, provision is made for the reference voltage (Uref) to be the variable of a function f(Uref) that has an extreme at the point where the selected nominal value (Uref.

Abstract: The present invention increases the difficulty of interpreting electromagnetic emissions from a keypad system by facilitating randomness in the electromagnetic emissions associated with a particular key activation. A keypad security circuit utilizes a set of digital values that varies over both time and the bits as a keypad driver word applied to a keypad attribute (e.g., a row or column). The keypad security system of the present invention drives the varying strong keypad driver signal to an attribute of a keypad switch matrix (e.g., the rows or columns), applies an independently configured weak driver signals to the opposing attribute of the keypad switch matrix, retrieves a resulting signal from the opposing attribute, and interprets the results to determine if a switch included in a keypad system was activated (e.g., a key is pressed).

Abstract: The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

Abstract: In an example embodiment, the semiconductor device comprises a carrier and a semiconductor element, such as an integrated circuit. The carrier is provided with apertures, thereby defining connecting conductors having side faces. Notches are present in the side faces. The semiconductor element is enclosed in an encapsulation that extends into the notches in the carrier. As a result, the encapsulation is mechanically anchored in the carrier. The semiconductor device can be made in a process wherein, after the encapsulating step, no lithographic steps are necessary.

Abstract: An LC oscillator (I) comprises a cross-coupled PMOS transistor pair (Ma, Mb) coupled to a pair of capacitors (Cva, Cvb) and a pair of inductances (La, Lb). To enhance the signal amplification of the oscillator, a pair of auxiliary transistor circuits (Qa, Qb; Na, Nb) is provided which are coupled between the drain and, preferably, the source of each PMOS transistor. The capacitors (Cva, Cvb) are preferably variable capacitors and the inductances (La, Lb) are preferably connected to ground to allow a enlarged tuning voltage range.

Abstract: The invention relates to a method and an arrangement for the verification of NV fuses as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for the detection of attacks on the smart card security which modify EEPROM contents and hence also the contents of EEPROM fuses. During the reset phase the fuses are read from the EEPROM. The fuse values successively read out are then automatically verified. One possible implementation is, for example, to load the fuse values read out into a signature register, followed by comparison with a reference value. Appropriate security measures can be activated should the automatic verification indicate an error, for example, due to unauthorized modification of a fuse or attack on the boot operation.

Abstract: A device contains a memory that stores a WOM codeword that encodes successive generations of data values. When the codeword must be updated to represent a new data value, the device determines which updates of the dataword can be realized by feasible single bit updates to the WOM (Write Once Memory) codeword. If no feasible single bit update is possible, feasible two-bit updates are considered. Under control of the new data values a connection circuit routes feasibility signals for various updates, that signal the single-bit feasibility of the updates. Routing brings together pairs of feasibility signals for updates that together produce a WOM codeword that encodes the new data value. A pair is selected in which both feasibility signals indicate feasibility and the codeword is updated according to the updates involved in the pair.

Abstract: The electronic device (10) comprises a capacitor (12) and an inductor (11) and is present on a substrate (1) with an unplanarized surface (2). This is realized in winding (21) of the inductor (11) has a thickness of at least 1 micron and has a planarized upper surface (81). The upper electrode (32) of the capacitor is present in a second electrode layer (6) and has a lower surface (82) which is spaced from the substrate (1) by a larger distance than the upper surface (81) of the lower electrode (31). The second electrode layer (6) preferably includes a second winding (22) of the inductor (11). The electronic device (10) is suitable for use at high frequencies.

Abstract: A semiconductor device, which is arranged in a semiconductor body (1), and which comprises at least one source region (4) and at least one drain region (5), each being of the first conductivity type, and at least one body (8) of the second conductivity type, arranged between source region (4) and drain region (5), and at least one gate electrode (10) which is isolated with respect to the semiconductor body (1) via an isolation layer (9). Said isolation layer (9) comprises polarizable particles, which are composed of a nanoparticulate isolating core and a sheath of polarizable anions or polarizable cations. The isolation layer (9) exhibits a high dielectric constant ?.

Abstract: Consistent with an embodiment of the present invention, there is a device for transferring a substantially disc-shaped workpiece from a workpiece carrier. The workpiece is fastened along a first one of its main surfaces with a double-side adhesive foil onto a carrier foil. The workpiece is fastened onto the carrier foil along a first one of the its main surfaces with a double-sided adhesive foil onto a carrier foil on whose surface the workpiece is to be provided and fastened along the first main surface in an at least substantially planar manner. The first double-sided adhesive foil is adhesively connected by a first adhesive layer provided on its first surface to a first surface of the workpiece carrier and by a second adhesive layer provided on it second surface to the workpiece alone the first main surface thereof.

Abstract: A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g.

Abstract: A phase lock loop comprises a variable frequency oscillator (20), a divider (30), a phase comparator (40), a gain control stage (240), and a loop filter (50). The frequency response of the loop is measured by superimposing a modulation at a number of different rates on the error signal generated by the phase comparator, and by measuring for each modulation rate the peak-to-peak variation of the loop control signal controlling the oscillator frequency. If, due to errors in component values, the frequency response deviates from its desired value, the loop gain is adjusted to bring the frequency response close to its desired value.

Abstract: The invention provides a method for reducing power dissipation in a power amplifier used in wireless communication systems, said power amplifier having transistors showing a quiescent current, wherein the quiescent current of the power amplifier is adaptively changed according to the average output power of the power amplifier. A power amplifier for use in wireless communication systems is provided, said power amplifier having transistors showing a quiescent current, comprises adaptive biasing means changing the quiescent current of the power amplifier in accordance with the average output power of the power amplifier for reducing power dissipation in the power amplifier. A UMTS hand set comprises a power amplifier as specified above.

Abstract: A method of manufacturing a semiconductor device comprising a silicon body (1) having a surface (4) provided with field isolation regions (2) enclosing active regions (3). In this method, on the surface of the silicon body there is formed an auxiliary layer (5) of a material on which, during an oxidation treatment, a thicker layer of silicon oxide is formed than on the silicon of the silicon body. Here, an auxiliary layer comprising silicon and germanium is formed on the surface, said auxiliary layer preferably being a layer of SixGe1?x?yCy, where 0.70<x<0.95 and y<0.05. Next, at the location of the field isolation regions to be formed, windows (9) are formed in the auxiliary layer and trenches (11) are formed in the silicon body. Next, on the walls (12) of the trenches, a silicon oxide layer (13) is provided and on the walls (10) of the windows a silicon oxide layer (14) is provided, both being formed by an oxidation treatment. The auxiliary layer is not oxidized throughout its thickness.

Abstract: A semiconductor device has an edge termination region (15) having a plurality of trenches (17). Conductive material (20) and insulating material (19) is formed at the trenches, and surface implants (21) are formed on either side of the trenches. A conductive bridge (23) connects the surface implants (21) to allow equilibrium to be reached in reverse bias.

Abstract: An RF power amplifier according to the invention comprises a plurality of parallel output transistors (HBT,1,1 to HBT,1,N) connected to a power supply. A plurality of base resistors (Rb,1,1 to Rb,1,N) for the output transistors (HBT,1,1 to HBT,1,N) and a plurality of input capacitors (Cb,1 to Cb,N), each coupled in parallel to receive an RF signal input and connected via at least one additional passive component to the inputs of each corresponding output transistor (HBT,1,1 to HBT,1,N), are provided An output for an RF output signal is obtained from the parallel connection of the output transistors (HBT,1,1 to HBT,1,N). The transistors (HBT,1,1 to HBT,1,N) are heterojunction bipolar transistors.

Abstract: A data processing device has load and store instructions which address memory with the content of a data pointer register. In a normal mode, the same data pointer register is used for all load and store instructions. In this mode the processor is compatible with a older processor design. In a special mode, at least two different registers are used alternately to address memory when memory access instructions are executed. A control register controls whether or not the different registers are updated as part of the memory access instructions. Preferably, the control register provides for more than one different kind of update of the different registers, such as post addressing increment, post addressing decrement etc.

Abstract: The invention relates to a mixing circuit for mixing a first signal RF with a second signal LO including a conversion stage T3 to convert the first signal RF into a current, a mixing core T1 and T2 to mix said current with the second signal LO, said mixing core being loaded via at least one load element ZC. Said circuit includes noise optimization means taking into account the contribution of the load element or elements ZC to the noise inversely proportional to the frequency that is present in the output signal. In particular the load elements can be selected from inductive resistors or silicon resistors or be constituted by resistors of a size selected to optimize the noise inversely proportional to frequency. The invention allows the production of mixers with very good performance at low frequency via a simple micro-electronic process of resistor forming.