Abstract: A bus communication system contains a pair of communication conductors and a driver. The driver contains a plurality of pairs of controlled current source circuit, each pair comprising current source circuits of a first and second, mutually opposite polarity, and a control circuit for matching currents drawn by the current sources in each pair. The current source circuit of the first polarity have outputs coupled to a first one of the communication conductors, the current source circuits of the second polarity have outputs coupled to a second one of the communication conductors. A delay line is provided, with taps coupled to control inputs of the current sources of the first and second polarity, so that the pairs are switched on successively with mutual delays between successive pairs, as determined by the delay line.

Abstract: The present invention provides a special structure of magnetic elements, e.g. MRAM elements, as a security device for IC's containing magnetic memory cells. In an example embodiment, the structure may comprise a combination of two or more associated magnetic elements with pre-set anti-parallel magnetization directions. By determining the polarisation directions of the magnetic elements, exposure to an external magnetic field can be detected. Inverse polarisation directions indicate a normal situation, aligned polarisation directions indicate that the MRAM-array has been exposed to an external field. In this way it can be detected whether a user has tried to erase or alter the data stored in the MRAM in an illegal way. The IC can regularly check the resistance of the security system during operation. Upon detection of a field exposure, the IC can erase all MRAM data, reset itself or, block its functioning.

Abstract: A delta sigma modulator is provided. The delta sigma modulator comprises quantitizer circuitry configured to generate a digital signal using a first analog signal and dither control circuitry configured to use the digital signal to adjust an amount of dither applied to the first analog signal.

Abstract: Typically, a bulk of the memory space utilized by an SOC (103) is located in cheaper off-chip memory devices such as Synchronous Dynamic Random Access Memory (SDRAM) memories (104). These memories provide a large capacity for data storage, at a relatively low cost. It is common for SOC devices to communicate with each other through these off-chip memory devices. Because of the large amount of data being processed on state of the art SOCs, the data bandwidth to and from the SDRAM memories is a critical source, which if improperly managed results in bottlenecks. Thus, a novel address mapping scheme, which has improved efficiency for two-dimensional memory transactions is proposed for mapping on-chip memory transactions. This novel mapping scheme aims to decrease these bottlenecks, by segmenting the data sequence into portions being smaller than the size of a row of a block of the SDRAM memories.

Abstract: A method of compiling byte code into native code disclosed together with a server (100) and a receiving terminal (101) for the same. The method comprises the steps of transmitting byte code files containing byte code from a server to a receiving terminal; transmitting grouping information relating to the grouping of byte code files to the receiving terminal; and compiling byte code files received at the receiving terminal to native code. The byte code files are selected for compilation as a function of the grouping of byte code files.

Abstract: The invention relates to an arrangement for generating a decoder clock signal for decoding a data signal which is available together with a clock signal and a data word signal signalizing data words, both of which signals may each have different frequencies. The arrangement comprises a phase control circuit (1) which receives the clock signal and supplies the decoder clock signal from its output, and which comprises at least one adjustable divider (14) which is preferably arranged at the input of the phase control circuit (1) and whose division ratio is adjustable.

Abstract: A circuit testing approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths. According to an example embodiment of the present invention, a configurator arrangement (100) is programmed to control a configured circuit (110), the control including automatically setting switches (115) on the configured circuit. In one implementation, the configurator arrangement is programmed to automatically detect test signals (i.e., digital and/or JTAG test signals) and to control switches (115) for routing test data along a test circuit path. With this approach, manual switching for routing the test signals is not necessary, which has been found to be useful in applications where access to the circuit paths for switching is difficult or impossible.

Abstract: A structure provides for the control of bond wire impedance. In an example embodiment, there is an integrated circuit device comprising a semiconductor device die having a plurality of grounding pads, signal pads, and power pads and a package for mounting the integrated circuit and includes a conductive path having at least one reference trace that surrounds the integrated circuit. A grounding arch is disposed over the semiconductor device die.

Abstract: The present invention relates to production testing of semiconductor devices, more specifically to production testing of such devices at wafer level. A method according to the present invention comprises the steps of generating (20) quality test-data at a limited number of semiconductor devices on the wafer, deciding (24) based on the generated quality test-data whether other semiconductor devices on the wafer are to be tested, and based on the result of the deciding step, testing (28) or not testing (26) the other semiconductor devices on the wafer. A corresponding wafer prober is also described.

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Abstract: Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (4), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly dielectric layer (8), a capping layer (6) and side-wall spacers (10), the cell further including source and drain contacts (22), wherein the fabrication includes: defining the floating gate stacks in the same processing steps to have equal heights; depositing over the floating gate stacks a poly-Si layer (12) with a larger thickness than the floating gate stacks' height; planarizing the poly-Si layer (12); defining the intermediate access gate (AG) in the planarized poly-Si layer (14) by means of an access gate masking step over the poly-Si layer between the floating gate stacks and a poly-Si etching step.

Abstract: An antenna arrangement comprises a patch conductor (102) supported substantially parallel to a ground plane (104). The patch conductor includes first (106) and second (108) connection points, and further incorporates a slot (202) between the first and second points. The antenna can be operated in a first mode when the second connection point is connected to ground and in a second mode when the second connection point is open circuit. By connection of a variable impedance (514), for example a variable inductor, between the second connection point and the ground plane, operation of the arrangement at frequencies between the operating frequencies of the first and second modes is enabled.

Abstract: A method of operating a telecommunication system that enables operation of a mobile telephone at different user rates that are dependent on the instantaneous location, where a local fixed station at the user end transmits a first signal of limited range that is received by a mobile telephone that is associated with the fixed station, that is, provided that the mobile telephone is present within the range of the transmission signal, and the mobile telephone transmits, in response to the reception of the first signal, a second signal to a base station of the telecommunication system which switches over to a different user rate in response to the reception of the second signal.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) and a substrate (2) comprising at least one semiconductor element (3) and provided with at least one connection region (4) and an overlying stripe-shaped connection conductor (5) which is connected to the connection region (4), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer (6), a hard mask layer (7), and a second dielectric layer (8) are deposited on the semiconductor body (1), where at the location of the connection region (4) to be formed, a via (44) is formed in the first dielectric layer (6) by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned photoresist layer deposited on top of the structure and at the location of the connection conductor (6) to be formed, a trench (55) is formed in the second dielectric layer (8) by means of plasma etching

Abstract: An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.

Abstract: A polysilicon silicide stringer fuse is constructed having a narrow width by using an overlay tolerance of the photo stepper tool instead of the minimum critical dimension tolerance of the stepper tool. In an example embodiment, a fuse (200) for integration within a semiconductor comprises depositing an insulating layer (205) adjacent to the semiconductor substrate (203). A silicon layer (201) is formed with a first silicon material having a first resistance deposited adjacent the insulating layer (205). The silicon layer has a first width. A metal silicide stringer (202), having a second resistance different from the first resistance is deposited over a portion of the first silicon material (201) and having a second width that is less than the first width within at least a portion thereof. The metal silicide conducts current therethrough with approximately the second resistance and agglomerates in response to a programming current other than the conduct current therethrough with a same second resistance.

Abstract: A driver circuit includes monitoring circuitry (32, 34, 36) for monitoring the states of high and low side switches (6, 8). The driver circuit has an adjustable delay for turning on the transistors (6, 8). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V1 before a voltage corresponding to the other transistor passes another predetermined point V2, and vice versa.

Abstract: A power converter includes a control device (28) for a switching power converter (10), a switching power converter and a method of controlling a switch in a power converter for reducing audible noise. The power converter includes the control device (28) and at least one switch (26) for regulating the power conversion. The control device (28) includes a timer (45) for monitoring a switching frequency of the switch (26) to indicate when the frequency has dropped to a certain level, and a gate driving circuit (32) connected to the timer and arranged to regulate the switching of the switch in dependence of the indication from the timer, so that the frequency rises above the certain level in order to reduce generation of audible noise.

Abstract: The invention relates to an electromechanical switching device including at least one pair of inductive elements electrically connected in series, said inductive elements being intended to generate two magnetic fields when current is flowing through said inductive elements, the interaction between these two fields resulting in a displacement of at least one of the inductive elements and a displacement of a mobile contact element linked to said at least one inductive element and intended to switch between two positions, at least one of these positions enabling an electrical connection between at least two conductive elements. The invention uses the mechanical forces exerted on at least one inductive element able to move thanks to two electro-magnetic fields oppositely generated by two inductive elements to activate a switch effect between two positions.

Abstract: A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step 114).