Abstract: A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.

Abstract: A method of splitting a signal (10) into two parts (10?, 10?) is disclosed together with signal processing circuitry (22) for the same. The method comprises the steps of derotating the signal (10) whereby the frequency band of the derotated signal overlaps zero frequency; and splitting the derotated signal into two parts, a first signal part (10?) consisting substantially of positive frequency signal components and a second signal part (10?) consisting substantially of negative frequency signal components. Also disclosed is methods, incorporating such a method of splitting a signal, for identifying the presence of in-band interference (11) in a signal and for despreading a spread spectrum signal.

Abstract: A test arrangement for testing the interconnections of an electronic circuit (100) and a further electronic circuit is provided. A first selection of I/O nodes (120), which are arranged to receive input data in a functional mode of the electronic circuit (100), and which are coupled to a test unit in a test mode of the electronic circuit (100). The test unit has a combinatorial circuit (160) for implementing a multiple-input XOR or XNOR gate. The test unit also provides interconnections between the first selection of I/O nodes (120) and a second selection of I/O nodes (130) via logic gates (141–144). These interconnections increase the interconnect test coverage of the electronic device (100), because the interconnects with the further electronic circuits that are associated with I/O nodes (131–134) become testable as well.

Abstract: The electronic device (100) is a chip-on-chip construction on a lead frame (10) comprising a heat sink (13) in an encapsulation (80). The first chip (20) and the second chip (30) are mutually connected by first conductive interconnections (24) and the first chip (20) is connected to the lead frame (10) by second conductive interconnections (27) which preferably have a lower reflow temperature than the first conductive interconnections (24). By heating the device (100) the adhesive layer (25) will first shrink, causing a stress, which will be relaxated by reflowing the second conductive interconnections (27).

Abstract: Receivers (1) for receiving encoded block signals and comprising processor systems (2) decode block signals by using Viterbi algorithms for finding a first candidate/path in a trellis (18) and by generating cost signals for finding further candidates/paths in said trellis (18). To reduce storage capacity, cost signals are combined for series of branches and cumulated cost is compared with thresholds. While searching for said further paths, a search for a further path is made in view of cumulated cost exceeding a threshold or not. The insight of indirectly constructing a list of candidates and the basic idea of more directly constructing said list brings more control. These receivers are less complex, and are further improved by introducing increasing thresholds per trellis and successive combining and different trellis directions for generating and cumulating cost signals and combining in a lexicographical order, and using a check sum for list reduction and by making error detections.

Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (11) in which an IC is formed and which has a number of connection regions (1) for the IC on its surface, including at least two connection regions (1A) for a supply connection, the lower side of the semiconductor body (11) being provided with a number of further connection regions (2) which are connected to a connection region (1) by means of an electric connection (3) which is present on a side face of the semiconductor body (11) and electrically insulated therefrom, and the semiconductor body (11) being attached to a lead frame (4) and wire connections (5) being formed between leads (4A) of the frame (4) and connection regions (1) .

Abstract: A data memory for storing elements, which data memory stores the data of the elements and at least a chained list which contains, for each stored element, at least its element address, its element number and a pointer to the address of the stored element having the next-higher element number. There are also provided an element status table, in which the element numbers of the elements present in the data memory are taken up, and also an address reference table which contains the element addresses for all element numbers.

Abstract: A GPS receiver is disclosed which has an omnidirectional antenna and a directional antenna and is configured to (i) acquire a first GPS signal from the output of the directional antenna, either alone or combined with the output of the omnidirectional antenna, and (ii) acquire a second GPS signal from the output of the omnidirectional antenna alone. Also, disclosed is a GPS receiver having an omnidirectional antenna and a directional antenna which is configured to acquire a GPS signal from the output of the directional antenna alone.

Abstract: A method and device are described for generating two output signals (I; Q) each substantially identical to a square-wave input signal (A) from a local oscillator (2), wherein the first output signal (I) may have a certain time shift with respect to the input signal (A), and wherein the second output signal (Q) is shifted over T1/4 [mod T1] with respect to the first output signal (I), T1 being the period of the input signal (A). To generate the first output signal (I), Fourier components (S1(?1), S3(?3), S5(?5), S7(?7), S9(?9), S11(?11) etc) of the input signal are combined. To generate the second output signal (Q), Fourier components (S1(?1), S5(?5), S9(?9) etc) of the input signal are phase shifted over +90° while Fourier components (S3(?3), S7(?7), S11(?11) etc) of the input signal are phase shifted over ?90°, and the thus shifted Fourier components of the input signal are combined.

Abstract: A method of operating a mobile telephone that is taken up in a data transmission network, which method involves at least one encoding and decoding algorithm for converting analog speech data into digital data and vice versa; according to this method at least one further encoding and decoding algorithm is transmitted to the mobile telephone via a data transmission link that is established between the mobile telephone and the network, which algorithm is received by the mobile telephone and stored in a non-volatile memory so as to be used for data conversion after the implementation.

Abstract: An integrated circuit has an input connection for connecting an external signal conductor that passes signals to execute functions in the device. The external signal conductor can pick up strong interfering signals with high frequency content, for example when the device is used in a car. To protect against unintended execution of functions the device contains a timer circuit comprising a capacitance and a current supplying circuit coupled to an integration node. A discharge diode is coupled between the input connection and the integration node, with a polarity such that the discharge diode, when in forward bias, is capable of draining current from the current supplying circuit. A detector is coupled to the integration node for generating a signal to be supplied to the integrated circuit device to respond to a signal transition on the conductor. The diode serves to reset integration on the integration node before the detector detects the transition in case of short pulses.

Abstract: A coupler (10) having a first line (1) and a second line (2) also comprises a resonant structure (3) including a capacitor (5) and an inductor (4). The coupler (10) thus delivers a coupling signal S31 that is substantially frequency independent over a frequency domain above the resonance frequency of the resonant structure (3). Also, the signal S31 has a high degree of directivity. The coupler (10) can be provided as part of an integrated electronic component, such as a multilayer substrate, a thin-film module or an IC. It can be applied in an electronic device (100) between a power amplifier (101) and an antenna (103). The coupling signal S31 will thus be provided to a controlling circuit (102).

Abstract: A portable device (1) includes a communication station configuration (10) for contactless communication with at least one external data carrier (13) and a data carrier configuration (11) for contactless communication with at least one external communication station (14), wherein a detection circuit (32) is provided which is designed to detect the presence of an external data carrier (13) and the presence of an external communication station (14) in a communication zone of the internal communication station configuration (10) and the internal data carrier configuration (11) designed for contactless communication, and wherein an activation circuit (33) cooperating with the detection circuit (32) is provided, by means of which activation circuit (33) one of the two configurations (10, 11) can be activated as a function of the detection result (INFO1, INFO2, INFO3) supplied in each case by the detection circuit (32).

Abstract: An antenna arrangement includes aground conductor (302) incorporating two slots (304a,304b) having an electrically small separation and connections (308a,308b) for coupling a transceiver to each slot to enable the ground conductor to function as two substantially independent antennas. Such a device enables efficient diversity performance to be obtained from small volume. The ground conductor, slots and transceiver are integrated in a module (206) adapted for connection to a further ground conductor which provides the majority of the antenna area. The further conductor would typically be a printed circuit board ground plane or mobile phone handset. Matching and broadbanding circuitry may conveniently be incorporated in the module. By varying the area of the connections between the module and the further ground conductor, the resonant frequencies of the slots can be modified.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: A power management system (100) comprising a power generator (1) for providing a supply signal (Vchg) to a load (2), a floating controllable bi-directional current sensor (N1) coupled via a first connection (10) to the power generator and via a second connection (20) to the load (2) for detecting a positive current (pos) flowing from the power generator (1) to the load (2) and a negative current (neg) from the load (2) to the power generator (3).

Abstract: A decoder system for concatenated codes such as turbo codes, comprises at least two component decoders mutually coupled through a reliability value handler for handling reliability values. The reliability value handler comprises a scaling unit for providing non linearly scaled reliability values. This reduces the reliability values provided by the component decoders, such that the non linearly scaled reliability values better reflect the genuine reliability information or Log Likelihood Ratio (LLR) in a practical realization of the decoder system generally having sub optimal component decoders.

Abstract: Mixer-systems for up/down-converting frequencies comprise many components: in case of balanced quadrature conversion, some parts will show a fourfold repetition (insight). By creating a three-phase mixer-system (10,40), less components will be necessary (basic idea). The sub-signals in the group of sub-signals at the sub-outputs have phase differences being present between two subsequent sub-signals within an interval of 100–140 degrees, which makes these sub-signals already (substantially) balanced. In case of said phase differences being each within an interval of 118–122 degrees, the sub-signals are even better balanced, and when being 120 degrees, the sub-signals are perfectly balanced. A group of transistors (11–13,14–16,17–19,41–43,44–46,47–49) per sub-input (1,2,3) switches and/or amplifies the sub-signals at the sub-inputs. In an active mixer-system (10), said groups of transistors (11–13,14–16,17–19) are switched by further transistors (20–22).

Abstract: The average current consumption of an electronic apparatus is determined in that an energy store C is repeatedly charged and discharged across the apparatus 1 between a set upper threshold value Uso and a set lower threshold value Usu during a typical operating sequence of the apparatus 1 and within a set measuring time T. The number N of charging processes occurring within the measuring time T is counted and the average current consumption is calculated therefrom while taking into account set values.

Abstract: A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) for storing settings of the data flow controlling elements (10) and an address decoder (40) for converting an address into selection signals for the memory cells (31a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30?). This provides for a reduction in memory area of the reconfigurable processing unit (1).