Abstract: A description is given of an arrangement for determining the position of a magnetic-field-sensitive sensor unit in the magnetic field of a magnet arrangement having an at least substantially bar-shaped contour along an at least substantially rectilinear motion coordinate that extends parallel to a longitudinal axis of the at least substantially bar-shaped contour, in which the magnetic-field-sensitive sensor unit is intended to measure a component of the magnetic field which extends in a plane that is at least substantially parallel to the longitudinal axis of the at least substantially bar-shaped contour in a manner at least substantially perpendicular to this longitudinal axis, and the magnet arrangement has a magnetic north pole in the region of a first end of the at least substantially bar-shaped contour, a magnetic south pole in the region of a second end of the at least substantially bar-shaped contour, and a narrowing of the at least substantially bar-shaped contour in the central region extending betw

Abstract: A DC-DC converter includes a switch (S1) which periodically connects an inductor (L) to a DC-input voltage (Vi) during an on-period (Ton) of a period time (Tp). The operating frequency (fo) of the DC-DC converter is the inverse of the period time (Tp). An output (O1) of the DC-DC converter is coupled to the inductor (L) to supply an output voltage (Vo). A controller (CO) controls the operating frequency (fo) of the DC-DC converter to be substantially proportional to the output voltage (Vo) to obtain a substantially constant average duration of the on-period (Ton) as function of the output voltage (Vo).

Abstract: A trench-gate semiconductor device (100) has a trench network (STR1, ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100).

Abstract: In order to improve a circuit arrangement (100) and a method of controlling at least one transistor (10, 12, 14, 18), especially of controlling the resistance value of at least one MOS transistor with vanishing DC modulation in such a way that a compensation of resistance variations without control deviation is also possible for the case where the transistor (10, 12, 14, 18) is operated with a vanishing DC voltage, i.e.

Abstract: A pseudo random generator comprising a shift register comprising a first flip flop (F0) and n further flip-flops (F1 . . . Fn) each flip-flop (F0) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F0) having a set input, each of the non-inverting outputs being connected via a NOR gate (10) to the set input of the first flip-flop (F0) and each of the non-inverting outputs of the flip-flops (F0 . . . Fn) being connected to the input of the first flip-flop (F0) via an XOR gate (11), characterised in that the generator comprises at least one additional logic gate (13, 14, 15; 17, 18, 19) including at least one additional flip-flop (14;18). The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra ‘0’ at the output or to chop, preferably randomly, the input signal.

Abstract: There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of ?90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.

Abstract: A method and a device (1) for detecting signal amplitudes by removing any DC component from the signal and then shifting the signal by a shift amount so as to produce a shifted signal having a first signal level equal to a reference level (Vref). The shift amount provides an indication of the amplitude of the signal. To this end, the device (1) includes a decoupling circuit (2), a shift circuit (3) and an output terminal (4). Optionally the device further includes a differential amplifier (5) coupled to receive the reference level (Vref) and an indication of the power of the shifted signal, and a signal power determination circuit (6) coupled between the shift circuit (3) and the differential amplifier (5).

Abstract: A GPS receiver device is disclosed comprising a GPS antenna and a GPS RF front-end including an analogue to digital converter for receiving GPS signals and outputting GPS signal samples; and a processor for encrypting the GPS signal samples and transmitting the encrypted GPS signal samples to an external device. Also disclosed is a corresponding method of providing a position fix comprising the steps of connecting to a GPS receiver device and receiving encrypted GPS signal samples therefrom, decrypting the encrypted GPS signal samples and processing the decrypted GPS signal samples to determine a position fix; and a computer program, computer-readable storage medium and apparatus for the same.

Abstract: A circuit architecture (200) for implementation of compensation based on Miller capacitors in multi-stage chopped amplifiers includes insertion of an additional chopper (206) in the compensation feedback (118, 120) pathway. Such compensation is more area efficient than parallel compensation and allows higher bandwidth in multistage amplifiers. The insertion of a chopper in the Miller capacitance feedback loop provides a means to selectively adjust the phase of the feedback by 180 degrees.

Abstract: A DC-offset correction circuit (I1, Q1) for a low-IF or zero-IF receiver, comprises a DC-offset control loop (O1, O2) embodied by: a summing device (9-1, 9-2) having a signal path input (10-1, 10-2), a DC control input (11-1, 11-2), and a summing output (12-1, 12-2); and an offset determining means (15-1, 15-2) coupled between the summing output (12-1, 12-2) and the DC control input of the summing device (9-1, 9-2). The DC-offset correction circuit (I1, Q1) further comprises a DC blocking circuit (17-1, 17-2) coupled to the summing output (12-1, 12-2) of the summing device (9-1, 9-2) and having a DC blocking output (18-1, 18-2) for providing an offset corrected output signal. The DC-offset control loop (O1, O2) and the DC blocking circuit (17-1, 17-2) advantageously interact in correcting DC offset.

Abstract: Antenna switches (1,10) in dual-band or multi-band mobile phones are according to a basic idea provided with a serial semiconductor switches (11,21,12,22) per transmitting branch (2,3) and with a further semiconductor switch (13,23) coupled in parallel to a receiving branch (4,5,6), to obtain isolation between branches (2-6) in a simple way. Said semiconductor switches are PIN diodes or MEMS switches or pHEMT switches. Another semiconductor switch (14) coupled in parallel to the receiving branches (4-6) allows together with said further semiconductor (13) the introduction of elements (15,16) without a transmission line. Alternatively, the antenna switch (1,10) may comprise a transmission line (24,25), in which case the receiving branches (4,5,6) can be switched via transistor switches (26,27,28). This all improves isolation, reduces costs, complexity, size and high Radio-Frequency (RF) losses.

Abstract: A protection circuit and method are provided for a floating power transfer device having one or more switches for controlling charging of a reservoir capacitor across which a load is applied when in use. The protection circuit includes a control circuit, a fault detection circuit and a precharge driver circuit. The control circuit at least partially controls switching of the at least one switch, while the fault detection circuit detects when a fault in the floating power transfer device or the load occurs and sends a fault detect signal to the control circuit in response thereto. The precharge driver circuit, which is enabled by the control circuit responsive to receipt of the fault detect signal, attempts to precharge the reservoir capacitor to a voltage level sufficient for switching of the one or more switches to proceed without damaging the switches.

Abstract: A down-converter for processing frequency signals, preferably received, particularly digital, television signals, comprising two, preferably identical mixer stages (10a, 10b) for down-converting the signal, a local oscillator (12) controlling the mixer stages by a 90° phase shift, a complex filter (14) which couples the output signals of the mixer stages (10a, 10b) by means of a complex filtering method in such a way that the signal components outside a predetermined useful band are substantially suppressed, an adjusting device (13) for adjusting the frequency of the local oscillator (12) and a subsequent low-pass filter.

Abstract: In order to further develop a circuit arrangement (100) for electronic data communication, comprising—at least a non-volatile memory module (10) for storing data, and—at least an interface logic (20) associated with the memory module (10)—for addressing the memory module (10) and—for writing data to the memory module (10) or—for reading data from the memory module (10), together with a related method for registering light attacks on the non-volatile memory module (10), in such a way that, firstly, the light attack is recognized immediately and reliably regardless of whether an access, in particular a read access, to the memory module (10) is taking place or not and, secondly, the entire address space of the memory module (10) is covered as uniformly as possible in this regard, it is proposed that at least a monitoring arrangement (22) provided for monitoring the memory module (10) is associated with the interface logic (20), by means of which monitoring arrangement (22) an irradiation of the memory module (10

Abstract: Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove into the semiconductor body for receiving the gate, and etching a second groove into the top major surface of the semiconductor body, the second groove extending from the first groove and being narrower than the first groove. The invention enables better control of the vertical extent of the gate below the top major surface of the semiconductor body.

Abstract: A three state class D amplifier (100) comprising a first signal path (1) and a second signal path (1?) substantially identical with the first signal path (1). Each of the signal paths (1, 1?) comprises respective first and second low-pass filter means (10, 10?) coupled to respective input signals (Vn, Vp) provided by input means (Inp, In, Ip), first and second ends (A, B) of a load (5) and to an pulse generator (2) providing a signal having a frequency substantially higher than a frequency of the input signals (Vn, Vp) for generating respective first and second low-pass filtered signals (SUP, SDW). The low-pass filtered signals (SUP, SDW) are inputted to respective comparing means (3, 3?).

Abstract: A duplexer (1) with two band-pass filters (5, 6) comprising film bulk acoustic wave resonators (FBAR) (8, 9, 10, 11, 12, 13) has an extra antiresonant circuit in order to block the transmission signal. It has an extra resonant circuit in order to allow the desired receive signal to pass. The antiresonant circuit comprises the first FBAR (11) and a parallel inductor (14). The resonant circuit comprises the first FBAR (11) and a series inductor (7).

Abstract: A technique includes providing a butter to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter to the buffer based on a status of the buffer. The techniciue may be used with a wireless system that includes a digital signal processor, a buffer, a wireless interface and a switch. The buffer receives data from the digital signal processor in response to an active mode of the digital signal processor. The switch selectively couples a terminal of the wireless interface to the buffer in response to a determination of a status of the buffer.

Abstract: An R-C oscillator (200) is configured to vary the two voltage levels that are used to control the oscillation, such that the variation in oscillation frequency with temperature is minimized. A first resistor (R1) is used to control one of the voltage levels, and a second resistor (R2) having a temperature coefficient that differs from the temperature coefficient of the first transistor is used to control the other voltage level. The first resistor (R1) also controls the current used to charge and discharge the capacitor (C) used to effect the oscillation. By the appropriate choice of resistance values, the variations of the control voltages and current are such that the time to charge and discharge the capacitor (C) between the control voltages remains substantially constant with temperature. Preferably the resistance values are selected to also compensate for temperature variations in the delay of the feedback loop.

Abstract: A portable communication device including a power control system which estimates Eb/Nt by determining the variance of the noise components of PCBs that are received on the fundamental traffic channel. The power control system includes a demodulator for demodulating a BPSK modulated (or PAM) first signal from a base station, a noise variance calculation circuit that samples the perpendicular noise component of the demodulated signal to determine a noise variance, a power estimation circuit that measures the power of the demodulated signal and provides an estimate of the power of the first signal by eliminating the noise variance from the demodulated signal, and a comparator that compares the ratio of the power estimate and the noise variance to a threshold. The comparator output is a power up or power down signal to the base station.