Abstract: Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of more than one supply voltage, the integrated circuit is subdivided into core functionality and peripheral functionality, and the carrier substrate is subdivided into a corresponding core area and peripheral area. The ground connections of both core and periphery are mutually coupled through an interconnect in the carrier substrate. This interconnect is particularly a ground plane, and allows the provision of a transmission line character to the interconnects for signal transmission of the periphery.

Abstract: A semiconductor device, for example a MOSFET or IGBT, includes a region (30, 36, 50) in the drain drift region (14) juxtaposed with its channel-accommodating region (15) and spaced from the drain contact region (14a) by means of an intermediate portion of the drift region. The region comprises alternating stripes (31, 32) of the first and second conductivity types, which stripes extend alongside the channel-accommodating region (15). In a trench gated device the stripes are elongated in a direction perpendicular to the trench walls. In a planar gate device the stripes extend around the periphery of the channel-accommodating region (15) leaving the region near the gate in a direction perpendicular with respect to the gate electrotes. The dimensions and doping levels of the stripes (31, 32) are selected such that region (30, 36, 50) provides a voltage-sustaining space-charge zone when depleted.

Abstract: A chopped intermediate frequency (IF) wireless receiver is disclosed. The wireless receiver includes a local oscillator (LO), a first and a second mixers, an LO frequency control module, an IF filter, a digital down converter and a down conversion controller. The LO provides a local oscillating signal to the first and second mixers. The first and second mixers converts a received radio frequency signal to an in-phase IF signal and a quadrature IF signal, respectively. The LO frequency control module alternately down converts a channel frequency by changing an oscillation frequency of the LO. Coupled to the digital down converter, the down conversion controller adjusts a complex sine wave within the digital down converter while the in-phase IF signal and the quadrature IF signal are being down-converted by the digital down converter to a baseband signal.

Abstract: The present invention relates to magnetic or magnetoresistive random access memories (MRAMs). The present invention provides an array with magnetoresistive memory cells arranged in logically organized rows and columns, each memory cell including a magnetoresistive element (32A, 32B). The matrix comprises a set of column lines (34), a column line (34) being cells of a column. A column line (34) is shared by two adjacent columns, the shared column line (34) having an area which extends a continuous conductive strip which is magnetically couplable to the magnetoresistive element (32A, 32B) of each of the memory cells of a column. A column line (34) is shared by two adjacent columns, the shared column line (34) having an area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line.

Abstract: A reconfigurable logic device according to the invention comprises a lookup table (LUT) (11.1) with an input (in 1) for receiving an input signal and an output (out) for providing a binary output signal. The reconfigurable logic device is characterized by, a control input (ctrl) for receiving a control bit, a controllable inverting gate (11.2) for providing the address signal to the LUT (11.1) in response to the control bit and the input signal, and by a controllable inverting gate (11.3) for providing a modified output signal in response to the output signal of the LUT and the control bit. The reconfigurable logic device according to the invention can operate at a high speed, and at the same time have a relatively modest configuration memory.

Abstract: An electronic circuit for providing a logic gate function includes a differential signal input, a combining stage, a discriminating stage and a differential signal output. The discriminating stage includes four transistors each having first electrodes and second electrodes and a respective gate electrode. The first electrodes of the four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of the four transistors respectively.

Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operation, the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract: The invention relates to a processing system comprising a calculation device comprising at least one calculation unit (13), a storage device and a system for switching between the storage device and the calculation device. In order to reduce the size of the switching system, the storage device comprises several banks of registers (21, 22) for storing words, the switching system comprises at least one switching device (24) associated with each bank of registers and the calculation units exchange a word with a bank of registers by means of the associated switching device.

Abstract: A filter structure, comprising a first signal line, a second signal line, a third signal line and a fourth signal line, said first and third signal lines defining an input port and said second and fourth signal lines defining an output port of a section of said filter structure, said section being defined by a first bulk acoustic wave resonator (A) which is connected between said first signal line and said second signal line, a second bulk acoustic wave resonator (G) which is connected between said third signal line and said fourth signal line, a third bulk acoustic wave resonator (C) which is connected between said first signal line and said fourth signal line, and a fourth bulk acoustic wave resonator (E) which is connected between said second signal line and said third signal line; is characterized in that a frequency pulling factor defined d of at least one of said acoustic wave resonators is non-zero, said frequency pulling factor d being defined by for first and second bulk acoustic wave resonators havi

Abstract: The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.

Abstract: The invention relates to a packet switching device with a plurality of input and output ports and at least one switching unit (3 to 5) comprising a coupling matrix and an arbiter unit (9) for controlling the coupling matrix (8), wherein the arbiter unit is designed for generating a state matrix (11) whose lines each correspond to an input port and whose columns each correspond to an output port, said state matrix comprises elements which each represent a weighting for an interconnection between an input port and an output port of the packet switching device, and said arbiter unit (9) is designed for forming a first decision matrix consisting of several accepted interrelationships on the basis of an algorithm which is operative in parallel on several groups (12 and 14) of columns of the state matrix.

Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).

Abstract: An operational amplifier includes a current provider that introduces an additional current Ic to an internal node A of the operational amplifier for reducing the output offset voltage of the operational amplifier.

Abstract: The present invention relates to a method of controlling a variable gain amplifier having at least one semiconductor switch, the amplifier having a first gain when the semiconductor switch is in a first steady state and a first gate voltage is applied to the semiconductor switch, and the amplifier having a second gain when the semiconductor switch is in a second steady state and a second gate voltage is applied to the semiconductor switch, whereby a sequence of third gate voltages is applied to the semiconductor switch to transition between the first and second gains.

Abstract: The present invention relates to a data processing circuitry and method of processing an input data pattern and out-putting an output data pattern after a processing delay which depends on a processing activity of the data processing circuitry, wherein the processing delay is estimated based on the input pattern and the processing is controlled in response to the estimated processing delay. The processing control may be a power control based on an activity monitoring or a clock control in a pipeline structure. Thereby, an efficient solution is provided to derive the current activity of the processing circuitry in order to dynamically adapt its operating conditions to its demands.

Abstract: The invention relates to a lead-frame configuration with a frame base and multiplicity of lead-frames connected with the frame base, of which each lead-frame is intended to hold a chip, where each lead-frame has two connection plates of which each is intended to connect with a connection of a chip, where the two connection plates of each lead-frame delimit a bridging zone which can be bridged using a chip.

Abstract: An amplifier/driver (40) for a bus has an output transistor (M1) that is controlled by a controlled current source (I1). In a quiescent state, the output transistor is configured as part of a current mirror (M1, M11) that maintains a gate-source voltage on the output transistor above the threshold voltage of the output transistor, thereby providing a fast turnon turn-on time. In an active state, the controlled current source provides a substantially constant current to the output transistor to achieve a controlled slew-rate, then reduces the current to the output transistor when a desired output voltage level is achieved. To improve power efficiency, a second controlled current source (I2) provides current to the output load when the desired output voltage level is achieved. To minimize transients, a class-AB control circuit (710) provides a minimum bias current to the output transistor, to prevent it from turning off when the desired output voltage level is achieved.

Abstract: The invention relates to a signal source (S) which comprises a local oscillator (5) for generating a reference frequency signal fo. The signal source comprises: a frequency divider by N (6) connected to the local oscillator (5) and delivering two quadratic square-wave signals (Id, Qd) at a frequency fo/N,N being equal to 2 or 4×n, and n being an integer number, and a multiphase filter (7) which supplies two sinusoidal quadratic signals (Is, Qs) at a frequency equal to m·fo/N on the basis of the quadratic signals (Id, Qd) issued by the frequency divider, m being an odd number. The invention finds its application in direct frequency conversion circuits and transmission circuits used in the field of telecommunication.

Abstract: The invention relates to a switching device comprising a plurality of inputs and outputs which are interconnected by an interconnection point matrix for transmitting electric signals supplied from the inputs to the outputs via transmission lines in accordance with a predefined switching plan. Each transmission line comprises a signal path for conveying the electric signals and a voltage reference path. The interconnection points are arranged in the matrix in such a way that two distinct transmission lines comprise one common voltage reference path. Application: packet switching in optical transmissions.

Abstract: In order to further develop a system (100) and a method for calibrating the clock frequency of at least one clock generator unit (38), in particular oscillator unit, that is assigned to at least one transmitting/receiving module (30), wherein—the transmitting/receiving module (30) communicates with at least one microcontroller unit (10) over at least one data line (20) and—the clock generator unit (38) is assigned at least one calibration unit (36), in such a manner that with significantly reduced system costs the clock frequency of the clock generator unit (38) can be calibrated with very high accuracy, it is proposed that—in order to calibrate the clock frequency of the clock generator unit (38) at least one calibration unit (36) is assigned to the clock generator unit 38), —the calibration unit (36) can be set in binary terms by means of at least one command signal (COM) via the data line (20), —the clock generator unit (38) is assigned at least one binary counter (34) that is clocked by the clock generato