Abstract: A controller is disclosed for a voltage regulator module including a power unit and providing an output current, Iout, at an output voltage, Vout, from an input current/voltage and being configured for use in a multi-module voltage regulator having a neighbouring voltage regulator module having a respective output connected in parallel, the controller comprising: a reference voltage source for providing a reference voltage; a current balancing unit, configured to receive a respective output current from the or each neighbouring voltage regulator module and to determine an adjusted reference voltage, from the reference voltage and for balancing the output current with the at least one respective output current; and a control unit configured to use the adjusted reference voltage to control the voltage regulator module, to provide the output current at the output voltage from the input current at the input voltage, based on adaptive voltage positioning regulation.

Abstract: A method for multiphase frequency to voltage conversion includes generating for each cycle of an oscillating input, one of a plurality of non-overlapping clocks. A respective voltage in proportion to an input frequency of the oscillating input, is generated in response to each of the non-overlapping clocks, with a respective one of a plurality of frequency to voltage converters. Each of the respective voltages is summated to generate a voltage sum proportional to the input frequency.

Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.

Abstract: A chip includes a plurality of ground conductors that at least partially surround a signal conductor on a same die. The signal conductor carries an interface (e.g., high speed) signal, and the ground conductors filter electromagnetic interference generated by the signal carried by the signal conductor. A chip package includes a plurality of ground pins around a signal pin that carries an interface signal. The ground pins filter electromagnetic interference generated by the signal carried by the signal pin. A printed circuit board includes a plurality of ground conductors around a signal line. The ground conductors are in vias and filter electromagnetic interference generated by an interface signal carried by the signal line.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for discharging an output capacitor of a power supply is disclosed. The power supply includes a primary side for receiving a signal to be converted and a secondary side for outputting a converted signal. The method involves detecting whether synchronous rectification (SR) circuitry at the secondary side is inactive, determining that the primary side is disconnected from a mains voltage when the SR circuitry is detected to be inactive, and discharging an output capacitor at the secondary side based on the determination that the primary side is disconnected from the mains voltage.

Abstract: Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighboring blocks and the I/O channels.

Abstract: A first communication device receives one or more physical layer (PHY) data units, which include a plurality of media access control (MAC) layer data units, from a second communication device via a communication channel that includes a first frequency segment and a second frequency segment separated by a gap in frequency, including simultaneously i) receiving a first MAC layer data unit via the first frequency segment of the communication channel, and ii) receiving a second MAC layer data unit via the second frequency segment of the communication channel. The first communication device generates acknowledgement information for the plurality of MAC layer data units, and transmits the acknowledgment information to the second communication device via one or both of i) the first frequency segment and ii) the second frequency segment.

Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.

Abstract: An integrated circuit (IC) includes a self-biased circuit and a start-up circuit for the self-biased circuit. The self-biased circuit generates a start-up indicator signal and an output signal. The start-up indicator signal indicates whether the self-biased circuit has started up. The start-up circuit includes a comparator, a start-up controller, and a peak controller. The comparator compares the start-up indicator signal with a reference signal generated based on supply voltages, and generates a comparison signal. The start-up controller controls a start-up of the self-biased circuit when the comparison signal is at a first logic state. Further, when the comparison signal transitions from the first logic state to a second logic state, the peak controller controls the output signal to maintain one of a voltage level and a current level of the output signal below a peak limit.

Abstract: An apparatus includes integrated circuitry (IC) and a further circuit. The IC includes internal circuits having sensitive/secret data (SSD) to be maintained as confidential relative to a suspect Hardware Trojan (HT) and including access ports through which information associated with the internal circuits is accessible by external circuitry associated with the HT. The further circuit to learn behavior of the internal circuits that is unique to the integrated circuitry under different operating conditions involving the internal circuits, involving the SSD and involving other data that is functionally associated with an application of the integrated circuitry.

Abstract: Methods for communications and of communication device involve determining a half-duplex communications mode for a communications device, and in response to determining the half-duplex communications mode for the communications device, disabling an echo canceller of the communications device and determining a time-division multiplex (TDM) communications schedule over a point-to-point communications link. In response to disabling the echo canceller and determining the TDM communications schedule over the point-to-point communications link, data transmission is conducted over the point-to-point communications link according to the TDM communications schedule without echo cancellation at the communications device. The TDM communications schedule specifies non-overlapping transmission time slots for different communications devices and a silent period for echo fade-out between consecutive transmission time slots of the non-overlapping transmission time slots.

Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.

Abstract: A bandgap reference voltage generator can include a bandgap core circuit configured to output at least one control voltage. The bandgap reference voltage generator can further include feedback circuitry that can be configured to receive a control voltage outputted by the bandgap core circuit or another control voltage generated based on the control voltage, and output a current. The current can be outputted such that the current is sourced to or sank from the bandgap core circuit. The feedback circuitry can be further configured to generate a bandgap reference voltage. When the current is sourced to the bandgap core circuit, the bandgap reference voltage can be greater than a threshold value. Similarly, when the current is sank from the bandgap core circuit, the bandgap reference voltage can be less than the threshold value.

Abstract: A method and apparatus are described for controlling the gain of a phase loop of an interleaved boost converter using cycle signals. In an embodiment, a phase compensator compares a duration of the power phase of a converter to a cycle duration for the converter to generate a phase compensation. A phase adjustment module receives phase feedback signals of the first and second converters, measures the phase difference, receives the phase compensation, and generates a phase control output in response. A cycle controller receives the phase control output and generates first and second drive signals to control switching of first and second gates of the respective converters, wherein times of the first and second drive signals are adjusted using the phase control output.

Abstract: There is described a device for determining an angle of arrival of a received RF signal, the device comprising (a) a first antenna and a second antenna arranged with a predetermined distance between them on an antenna axis, the first antenna having a larger gain than the second antenna for directions corresponding to one side of the antenna axis, the second antenna having a larger gain than the first antenna for directions corresponding to the other side of the antenna axis, (b) receiver circuitry coupled to the first antenna and to the second antenna, the receiver circuitry being configured to determine a first phase and a first signal strength of a signal received by the first antenna and to determine a second phase and a second signal strength of a signal received by the second antenna, and (c) angle determining circuitry configured to determine the angle of arrival based on the first phase, the second phase, the first signal strength, and the second signal strength.

Abstract: A radio frequency amplifier includes a transistor, an input impedance matching circuit (e.g., a single-section T-match circuit or a multiple-section bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input terminal. An input of the fractional harmonic resonator circuit is coupled to the amplification path input, and an output of fractional harmonic resonator circuit is coupled to the transistor input terminal. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency that is between a fundamental frequency of operation of the RF amplifier and a second harmonic of the fundamental frequency. According to a further embodiment, the fractional harmonic resonator circuit resonates at a fraction, x, of the fundamental frequency, wherein the fraction is between about 1.25 and about 1.9 (e.g., x?1.5).

Abstract: Various embodiments relate to a method for multiplying a first and a second polynomial in the ring [X]/(XN?1) to perform a cryptographic operation in a data processing system, the method for use in a processor of the data processing system, including: receiving the first polynomial and the second polynomial by the processor; mapping the first polynomial into a third polynomial in a first ring and a fourth polynomial in a second ring using a map; mapping the second polynomial into a fifth polynomial in the first ring and a sixth polynomial in the second ring using the map; multiplying the third polynomial in the first ring with the fifth polynomial in the first ring to produce a first multiplication result; multiplying the fourth polynomial in the second ring with the sixth polynomial in the second ring to produce a second multiplication result using Renes multiplication; and combining the first multiplication result and the second multiplication result using the map.

Abstract: The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

Abstract: A system and method for correcting image distortion is provided. The system and method remaps pixel position of distorted images using a combination of radial distortion correction and tangential distortion correction lookup tables consuming less physical memory. The solution conserves both memory and memory access bandwidth. The radial distortion correction lookup table is formed by taking advantage of radial distortion being generally symmetric about a determined optical center of the camera lens. This symmetry allows for use of a quarter LUT for correction in all quadrants of a distorted image. In addition, tangential distortion can be corrected in a symmetric manner that saves memory space as well.