Patents Assigned to NXP
  • Patent number: 11463055
    Abstract: An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit with a first inductor and a first capacitance in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a shunt-L circuit. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitance in series between the amplifier output and ground. The shunt-L circuit includes a fourth inductor and a third capacitance connected in series between the amplifier output and ground.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP USA, Inc.
    Inventors: Wenming Li, Tong Qiao, Yunfei Wang
  • Patent number: 11463198
    Abstract: A security module (434) for a serial communications device. The security module (434) comprising: a receive data, RXD, input interface (436) for receiving data from a serial communications bus (404); and a transmit data, TXD, output interface (438) for transmitting data to the serial communications bus (404). The security module (434) is configured to: receive a message (540) from the serial communications bus (404) via the RXD input interface (436); compare the message (540) with one or more error conditions; and upon detection that an error condition has been violated, output an error-signal (543) to the serial communications bus (404) via the TXD output interface (438), wherein the error-signal (543) identifies one or more parameters relating to the error condition.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP B.V.
    Inventor: Bernd Uwe Gerhard Elend
  • Patent number: 11460522
    Abstract: A resistive sensor system includes resistive sensor pairs formed of first and second sensors of opposite sensitivity directions to a measured property. Each resistive sensor pair includes one of the first sensors having a first terminal and a second terminal, and one of the second sensors having a third terminal and a fourth terminal. The fourth terminal is coupled to the second terminal of the first sensor. The system further includes multiple noninverting switch elements, each having a noninverting output coupled to the first terminal of one the first sensors, and multiple inverting switch elements, each having an inverting output coupled to the third terminal of one of the second sensors. For each resistive sensor pair, the noninverting and inverting switch elements receive a switch signal for controlling the noninverting and inverting switch elements such that the first and second sensors are biased in opposition to one another.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP B.V.
    Inventors: Edwin Schapendonk, Hendrikus van Iersel, Maciej Skrobacki
  • Patent number: 11460566
    Abstract: A receiver unit is disclosed for use in a multiple-input-multiple output, MIMO, radar system having a plurality of transmitters each for transmitting one of a group of orthogonal digital-transmitter-signals on a carrier wave, the receiver unit configured and adapted to receive a raw-analog-signal on a carrier wave reflected from one or more target objects.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 4, 2022
    Assignee: NXP USA, Inc.
    Inventors: Gustavo Guarin Aristizabal, Ralf Reuter, Maik Brett
  • Patent number: 11460567
    Abstract: Aspects of the present disclosure are directed to radar signaling utilizing a non-uniform multi input/multi output (MIMO) antenna array including first and second uniform MIMO antenna arrays respectively having both sparsely-arranged transmitting antennas and sparsely-arranged receiving antennas. Communication circuitry is configured to determine a direction of arrival of reflections of radar signals transmitted by the transmitting antennas and received by the receiving antennas, by comparing the reflections received by the first MIMO array with the reflections received by the second MIMO array during a common time period (e.g., at the same time). Using this approach, the antenna arrays may be utilized to provide co-prime spacing/elements and to suppress ambiguities in received reflections based on alignment thereof.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP B.V.
    Inventors: Navid Amani, Alessio Filippi, Feike Guus Jansen
  • Patent number: 11460969
    Abstract: A mutually capacitive touch sensor includes a first capacitor electrode and a second capacitor electrode. The second capacitor electrode is adjacent and spatially separated from the first capacitor electrode. An inner region is disposed between the first capacitor electrode and the second capacitor electrode, wherein the first capacitor electrode and the second capacitor electrode are arranged to surround the inner region. The inner region may include a hole for a backlight.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: October 4, 2022
    Assignee: NXP USA, Inc.
    Inventors: Yong Su, Yonggang Chen, Wenwei Jiang
  • Patent number: 11463134
    Abstract: Wi-Fi communication is further secured by perturbation of a spatial mapping matrix. In an embodiment channel state information is obtained from a receiving device in a wireless network through the wireless network. A first set of beam steering vectors is derived based on the channel state information to direct a radio signal to the receiving device. A second set of beam steering vectors is derived based on the channel state information to direct a radio signal other than to the receiving device. A perturbation matrix is generated. A spatial mapping matrix is formed by combining the first and the second set of beam steering vectors with a perturbation matrix. Data symbols to be transmitted are pre-coded to the receiving device using the spatial mapping matrix and transmitted through the wireless network to the receiving device.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: October 4, 2022
    Assignee: NXP USA, INC.
    Inventors: Sayak Roy, Ankit Sethi, Sudhir Srinivasa
  • Patent number: 11463056
    Abstract: An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjust circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP USA, Inc.
    Inventors: Carmelo Morello, Hanqing Xing, Ranga Seshu Paladugu, Soon G. Lim
  • Patent number: 11460542
    Abstract: Multi-channel radio frequency (RF) transmitter (100) and method of calibrating the transmitter are provided.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: October 4, 2022
    Assignee: NXP USA, INC.
    Inventors: Olivier Vincent Doare, Stephane Damien Thuries, Gilles Montoriol
  • Patent number: 11461205
    Abstract: An error management system can include register sets associated with an error reaction. The test errors are injected in functional signals based on activation of multiple bits in one of the register sets. When the functional signals with the injected test errors are received by the error management system, multiple bits in the other register set are activated. The error management system generates an activated indication signal when a number of the activated bits in one register set matches a number of activated bits in the other register set. When the indication signal is activated, the error management system generates a reaction signal indicative of the error reaction. Thus, the error management system generates a single reaction signal in response to the injected test errors requiring the same reaction.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 4, 2022
    Assignee: NXP B.V.
    Inventors: Neha Bagri, Abhinav Gaur, Nipun Mahajan
  • Patent number: 11463101
    Abstract: The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: October 4, 2022
    Assignee: NXP B.V.
    Inventors: Chenming Zhang, Lucien Johannes Breems, Muhammed Bolatkale
  • Patent number: 11462493
    Abstract: An electrostatic discharge (ESD) protection scheme is provided that reduces EMI noise propagation among functional circuit blocks of an integrated circuit (IC). Traditional ESD protection schemes include an ESD bus electrically tied to the substrate of an integrated circuit (e.g., a P-well) and substrate well regions associated with electromagnetic interference (EMI) aggressor and sensitive circuits. These electrical couplings can propagate EMI noise on the ESD bus throughout the circuit blocks of the IC. Embodiments provide an ESD bus that is not tied to the substrate well regions associated with EMI aggressor and sensitive circuits of the IC, but instead is a separate conductive layer electrically coupled to an external ground. In this manner, the device circuits are isolated from EMI noise carried in the ESD bus, thereby protecting the various functional blocks from such noise.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP USA, INC.
    Inventors: Radu Mircea Secareanu, Michael A. Stockinger
  • Patent number: 11461642
    Abstract: An apparatus for processing a signal for input to a neural network, the apparatus configured to: receive a signal comprising a plurality of samples of an analog signal over time; determine at least one frame comprising a group of consecutive samples of the signal, wherein the or each frame includes a first number of samples; for each frame, determine a set of correlation values comprising a second number of correlation values, the second number less than the first number, each correlation value of the set of correlation values based on an autocorrelation of the frame at a plurality of different time lags; provide an output based on the set of correlation values corresponding to the or each of the frames for a neural network for one or more of classification of the analog signal by the neural network and training the neural network based on a predetermined classification.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: October 4, 2022
    Assignee: NXP B.V.
    Inventors: Jose De Jesus Pineda de Gyvez, Hamed Fatemi, Emad Ayman Taleb Ibrahim
  • Publication number: 20220310456
    Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: NXP B.V.
    Inventors: Mark Douglas Hall, Tushar Praful Merchant, Anirban Roy
  • Publication number: 20220310786
    Abstract: A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: NXP B.V.
    Inventors: Tushar Praful Merchant, Mark Douglas Hall, Anirban Roy
  • Patent number: 11456188
    Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 27, 2022
    Assignee: NXP USA, INC.
    Inventors: You Ge, Meng Kong Lye, Zhijie Wang
  • Patent number: 11455026
    Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: September 27, 2022
    Assignee: NXP USA, Inc.
    Inventors: Loic Hureau, Jean-Philippe Meunier, Daniel McKenna
  • Patent number: 11457346
    Abstract: An electronic device and a method for managing an IC card with multiple SIM profiles is described. The electronic device comprises: i) an integrated circuit (IC) card domain, configured to store a first SIM profile and a second SIM profile, and ii) a communication domain coupled to the IC card domain via a physical interface. The IC card domain is configured to: a) generate a first logical interface on the physical interface and associate the first SIM profile with the first logical interface by providing a first logical interface identifier, and b) generate a second logical interface on the physical interface and associate the second SIM profile with the second logical interface by providing a second logical interface identifier.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 27, 2022
    Assignee: NXP B.V.
    Inventors: Giten Kulkarni, Christian Paul, Shameer Puthalan
  • Patent number: 11456227
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 27, 2022
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Patent number: 11457448
    Abstract: A method and an apparatus for operating a Basic Service Set (BSS) are disclosed. A method involves announcing, by a first wireless device to a second wireless device, a BSS operating channel, wherein the first wireless device has at least one of a first transmission power capability and a first bandwidth capability, the second wireless device has at least one of a second transmission power capability that is less than the first transmission power capability and a second bandwidth capability that is narrower than the first bandwidth capability, and wherein the BSS operating channel is at least one of a punctured operating channel and an unpunctured operating channel, associating, by the second wireless device, with the first wireless device via the announcement of the BSS operating channel from the first wireless device, and exchanging frames between the first wireless device and the second wireless device in the BSS operating channel.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 27, 2022
    Assignee: NXP USA, Inc.
    Inventors: Liwen Chu, Rui Cao, Sudhir Srinivasa, Hongyuan Zhang, Huiling Lou, Young Hoon Kwon