Abstract: A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.

Abstract: A mechanism is provided for determining an unambiguous direction of arrival (DoA) for radio frequency (RF) signals received by a sparse array. A DoA angle domain is split into hypothesis regions. The hypothesis regions are derived from the phase differences of the antenna element pairs used for the DoA angle estimate. In each hypothesis region, the ambiguous phase of antenna element pairs is unwrapped according to expected wrap-around. After unwrapping the phase, for each hypothesis region, a phasor is calculated by combining the individual antenna element pair phasors. The hypothesis region that obtains the phasor with a largest amplitude is selected as the most likely DoA region and the phase of the winning phasor is used as an unambiguous estimate for the DoA angle.

Abstract: A method and system are provided to resolve Doppler ambiguity and multiple-input, multiple-output array phase compensation issues present in Time Division Multiplexing MIMO radars by estimating an unambiguous radial velocity measurement. Embodiments apply a disambiguation algorithm that dealiases the Doppler spectrum to resolve the Doppler ambiguity of a range-Doppler detection. Phase compensation is then applied for corrected reconstruction of the MIMO array measurements. The dealiasing processing first forms multiple hypotheses associated with the phase corrections for the radar transmitters based on a measured radial velocity of a range-Doppler cell being processed. A correct hypothesis, from the multiple hypotheses, is selected based on a least-spurious spectrum criterion. Using this approach, embodiments require only single-frame processing and can be applied to two or more transmitters in a TDM MIMO radar system.

Abstract: An apparatus comprising an acoustic transducer arrangement configured to transmit at least one acoustic signal and configured to detect a reflection of said at least one acoustic signal, and a controller configured to determine a time-of-flight of the at least one acoustic signal, the controller further configured to determine at least a first value indicative of temperature based on said time-of-flight of the at least one acoustic signal and calibration information indicative of a relationship between time-of-flight and temperature in a space the apparatus is located.

Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.

Abstract: An active shielding device and method for active shielding are disclosed. The active shielding device includes current sources configured to generate currents, an analog wire shield unit connected to the current sources, a current to voltage converter connected to the analog wire shield unit and configured to generate a voltage in response to the currents that are generated by the current sources, and a voltage comparator connected to the current to voltage converter and configured to compare the voltage that is generated by the current to voltage converters with a reference voltage.

Abstract: A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.

Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.

Abstract: A temperature compensated, auto tunable, frequency locked loop oscillator includes, in one embodiment, an oscillator configured to generate a clock-signal with a frequency fclk based on a control voltage vc, and a frequency-to-voltage (f/v) converter coupled to the oscillator, which is configured to generate a first voltage vfb with a magnitude based on frequency fclk. A controller is also included and coupled between the oscillator and the f/v converter. The controller is configured to control the magnitude of the control voltage vc based on the first voltage vfb.

Abstract: A device includes a substrate, an insulating layer that includes an etch stop layer formed over an upper surface of the substrate, a first conductive region formed over the insulating layer, and an opening formed within the substrate that extends from a lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region. A method for forming the device includes forming the substrate, forming the insulating layer that includes the etch stop layer over the upper surface of the substrate, forming a first conductive region over the insulating layer; and forming an opening within the substrate that extends from the lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region formed over the insulating layer.

Abstract: A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors (61) and MEMS sensors (62) in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (12A-16A, 12B-16B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (49A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (13B-2, 15B-2) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (13B-1, 15B-1) on a second side of the MEMS sensor stack by forming a narrow trench opening (54) in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

Abstract: Duty cycles of pulse width modulation (“PWM”) pulses are determined by measurements taken with respect to an internally generated clock signal. One of these measurements calculates, in a continuous dynamic manner, a ratio of the number of cycles of the internally generated clock signal to one or more cycles of a PWM clock signal utilized as a time base for generation of the PWM pulses. This clock ratio measurement designates how many cycles of the internally generated clock signal will be used to designate a first portion of a duty cycle for each PWM pulse. Another measurement is utilized to determine a fractional portion of a cycle of the internally generated clock signal that will be used to designate a second portion of the duty cycle for each PWM pulse.

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (11-18) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (25A, 25B) and to form gate electrodes (33A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g., 37/39, 25/55, 64/69) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

Abstract: Exemplary aspects are directed to transceivers interlinked in a communication system, for example, in respective circuit-based nodes installed in battery-operated vehicle or other apparatus. Representative of the communication system are a first transceiver and a second transceiver which communicate with one another over a communication link, with the first transceiver initiating a request over the link to the second transceiver. The second transceiver may receive the request and, for a period of time in response to receiving to the request, monitor the link to detect whether any further signaling on the link by the first transceiver indicates to accept the request. In certain other more specific examples, the above aspects are used as part of a handshake protocol to mitigate delays and related issues in coordinating timely actions associated with the request.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: UAV airways system generally are disclosed. Such UAV airway systems may comprise UAV cargo transportation systems and UAV surveillance and monitoring systems. Such systems preferably overlay and are commensurate with a system of high-voltage power transmission lines of high-voltage transmission system, and electric field actuated (EFA) generators preferably are utilized in UAVs that travel along the transmission lines, in UAV charging stations located along the transmission lines, or in both. Each EFA generator represents a power supply and comprises first and second electrodes separated and electrically insulated from each other for enabling a differential in voltage at the first and second electrodes resulting from a differential in electric field strength experienced by the first and second electrodes arising from the power transmission lines of the high-voltage transmission system.

Abstract: A beamformer generates a null data packet (NDP) that includes various long training fields (LTFs). The beamformer generates the NDP based on a spatial mapping matrix that is a product of two matrices. One matrix has a number of rows equal to a number of antennas of the beamformer, and a number of columns equal to a number of LTFs in the NDP. Further, the other matrix has a number of rows and a number of columns equal to the number of LTFs in the NDP. The number of LTFs in the NDP is greater than a number of antennas of the beamformer. Further, the beamformer transmits the NDP to a beamformee to obtain channel state information associated with a channel between the beamformer and the beamformee, and enable beamforming therebetween.

Abstract: An arbitration between a plurality of flows for access to a shared resource is disclosed. The plurality of flows may be associated with a single channel or multiple channels. When the plurality of flows are associated with a single channel, one flow is selected from the plurality of flows for accessing the shared resource based on flow priority levels associated with flows that are currently arbitrating for the access. Flow data associated with the selected flow is then outputted for granting the access. When the plurality of flows are associated with multiple channels, a flow associated with each channel is selected based on the flow priority levels. Further, a channel is selected based on channel priority levels of channels that are currently arbitrating for the access. Based on the selected channel, flow data associated with one of the selected flows is outputted for granting the access to the shared resource.

Abstract: A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode.