Abstract: A wireless local area network (WLAN) system includes a multi-access point (multi-AP) controller configured to onboard, authenticate, and configure respective basic service sets (BSSs) of access points in a multi-AP network. A plurality of access points (APs), including at least a first AP and a second AP, communicate with the multi-AP controller over a backhaul network, and in response to instructions conveyed by the multi-AP controller over the backhaul network, associate and communicate with client stations (STAs) over wireless fronthaul links in the WLAN system using the respective BSSs configured by the multi-AP controller. The first AP and the second AP are configured to request and receive at least one cryptographic value from the multi-AP controller, and to apply the at least one cryptographic value in securing a message transmitted over the backhaul network from the first AP to the second AP.

Abstract: Disclosed is a method of wireless communication between a vehicle base station and a transponder, the method comprising: i) driving first and second antennae on the vehicle by the vehicle base station using first driving currents, the first antenna being separated from the transponder by a portion of a vehicle in which the vehicle base station resides; ii) detecting three separate mutually orthogonal vector components of the respective fields emitted by the first and second antennae and received at the transponder; iii) calculating superposition factors for the first and second antennae based upon the separate vector components; iv) concurrently driving the first and second antennae using the same phase, respectively using the first driving currents multiplied by the calculated superposition factors; v) detecting three mutually orthogonal vector components of a superposed signal including signals from both antennae received at the transponder; vi) determining whether two of the three detected vector component

Abstract: A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.

Abstract: An angle of arrival (AoA) of an electromagnetic wave is determined. A phase of an antenna signal associated with each of two receive antenna is measured. A measured phase difference of arrival (PDoA) of the electromagnetic wave is determined based on the measured phase of each of the antenna signals. The measured PDoA is corrected based on one or more crosstalk factors associated with the two receive antennas. The AoA of the electromagnetic wave at the two receive antenna is generated based on the corrected measured PDoA.

Abstract: A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal.

Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver. The transceiver is configured to detect a CRC delimiter or an error signal in a CAN frame and after the detection, allow a microcontroller coupled with the microcontroller port to only send a predetermined data pattern until a bus idle is detected.

Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.

Abstract: A transceiver includes a transmitter, a frequency synthesizer coupled to the transmitter, a receiver coupled to the frequency synthesizer and a voltage sensor; and a digital controller coupled to the voltage sensor, the receiver, and the transmitter, wherein based on a DC voltage measurement of an IF signal made by the voltage sensor, a relative phase adjustment occurs of a relative phase associated with a local oscillator (LO) port and a radio frequency (RF) port of the receiver.

Abstract: A communication device stores a master rate table, which comprises a plurality of rows that correspond to i) respective data rates, and ii) respective sets of communication parameter values corresponding to the respective sets of data rates. Each set of communication parameter values includes i) a default value of a parameter, and iii) one or more alternative values of the parameter. When the communication device determines that a new transmission rate should be used, and when a current set of communication parameter values corresponds to a row in the master rate table and includes the default value, the communication device selects a trial set of communication parameter values corresponding to the row of the master rate table, and including one of the alternative values. The communication device measures an error rate measure corresponding to use of the trial set of communication parameter values.

Abstract: A mechanism is provided for estimating mounting orientation yaw and pitch of a radar sensor without need of prior knowledge or information from any other sensor on an automobile. Embodiments estimate the sensor heading (e.g., azimuth) due to movement of the automobile from radial relative velocities and azimuths of radar target detections. This can be performed at every system cycle, when a new radar detection occurs. Embodiments then can estimate the sensor mounting orientation (e.g., yaw) from multiple sensor heading estimations. For further accuracy, embodiments can also take into account target elevation measurements to either more accurately determine sensor azimuth and yaw or to also determine mounting pitch orientation.

Abstract: An on-chip low-voltage current sensing circuit for measuring current in an integrated circuit (IC). In one embodiment, an IC formed on a substrate, which includes a plurality of subcircuits, and a plurality of sensing circuits coupled to the plurality of subcircuits, respectively. The plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively, consumed by the plurality of subcircuits, respectively, during operation thereof. A circuit is coupled to the plurality of sensing circuits and configured to generate a signal based on an aggregate of the plurality of currents.

Abstract: A scan flip-flop includes a selection circuit, a primary latch, a secondary latch, and a data retention latch. The selection circuit selects and outputs one of functional data, first reference data, scan data, and first control data as second reference data. The primary latch receives the second reference data and outputs third reference data, whereas the secondary latch receives the third reference data and outputs second control data. The second control data is then provided to a subsequent scan flip-flop of a scan chain. The data retention latch receives one of the third reference data and the second control data, and outputs and provides the first reference data to the selection circuit. The first reference data corresponds to functional data retained in the scan flip-flop during a structural testing mode associated with the scan chain.

Abstract: Testing of the noise-shaping circuitry within a successive approximation register (“SAR”) analog-to-digital converter (“ADC”) (“SAR ADC”) to ensure it will function as expected, while also providing a method for calibrating the coefficients of the noise-shaping circuitry. Programmable/trimmable circuit component(s) can be used to calibrate the coefficient(s) of the SAR ADC. Digital logic within the SAR engine enables it to selectively skip portions of the ADC conversion process and to use voltage references rather than an analog voltage input signal in sample mode during such test/calibration modes.

Abstract: A system-on-chip (SoC) includes multiple critical components and a testing system to test the critical components. The critical components include an intellectual property (IP) core and an associated logic circuit. The testing system includes a controller, a fault injector, and a masking circuit. The controller is configured to receive a test initiation request and generate first and second select instructions. The fault injector is configured to generate and inject a set of fault inputs in the logic circuit based on the first select instruction to test the associated logic circuit and the IP core. The IP core is configured to generate a set of responses that is associated with the testing of the logic circuit and the associated IP core. The masking circuit is configured to mask and output the set of responses when the second select instruction indicates a first value and a second value, respectively.

Abstract: An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.

Abstract: A measurement apparatus comprising a first terminal to receive an input signal of a circuit under test; a second terminal to receive an output signal of the circuit under test. A first and second phase splitter configured to generate a first and second phase signal, I1 and I2, and a first and second quadrature signal, Q1 and Q2. A first and second multiplexer, each coupled to the first terminal and the second terminal and configured to alternately pass the input and output signals of the circuit under test to the inputs of the first and second phase splitters. A double-quadrature mixer having four inputs configured to receive I1, Q1, I2, and Q2, and an output. A calculation unit to determine one or both of a phase shift of the circuit under test and/or a gain of the circuit under test based on the output of the double-quadrature mixer.

Abstract: An integrated circuit, can comprise a first power supply terminal configured to supply a first voltage, a second power supply terminal configured to supply a second voltage, a first supply monitor including a detector having a first input and a second input, and configured to provide a fault indicator based on a comparison between the first and second inputs, and switching circuitry configured to during a normal operating mode, couple a voltage derived from the first voltage to the first input and a voltage derived from the second voltage to the second input, and during a self-test mode, couple the voltage derived from the second voltage to the first input and the voltage derived from the first voltage to the second input.

Abstract: A PID loop filter control method and apparatus are provided for generating a control signal to control a digitally controlled oscillator which generates a phase locked loop clock signal, where the PID loop filter includes a proportional-integral-derivative (PID) controller connected and configured to produce a PID controller output signal, and a transformed feedback module having a feedback summer circuit and internal gain stage connected in series to produce an M-bit control signal in response to the PID controller output signal, wherein an output from internal gain stage is provided over a feedback path comprising a feedback gain stage having a configurable Kfb gain value (e.g., 0<Kfb<4) and a filter element to produce the internal feedback signal which is summed with the PID controller output signal to low pass filter high frequency spurs and noise from the PID controller output signal.

Abstract: A wireless ranging system (700) estimates a distance (703) between wireless devices (701, 702) by calibrating the devices through exchanging calibration packets (512, 524) to adjust transceiver settings for performing phase measurements at the wireless devices, and then transmitting a measurement packet (704) from a first wireless device to a second wireless device to synchronize the first and second wireless devices and to perform a two-way IQ data capture sequence at different carrier frequencies during processing of the measurement packet so that the first and second wireless devices each measure phase values for each of the plurality of different carrier frequencies, where the phase values at each of the first and second wireless devices are processed to generate a combined phase offset vector which is processed to determine a first estimated distance between the first and second wireless devices.

Abstract: An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.