Abstract: Accordingly, systems and methods for managing power when the number of training and data tones are increased in a wireless communications system are provided. An L-SIG field is generated that includes a set of data and pilot tones, wherein the pilot tones are inserted between the data tones in the set of data and pilot tones. A plurality of training tones is added to the L-SIG field before and after the set of data and pilot tones. A symbol is generated that includes the L-SIG field, an L-LTF field, and a data field, wherein the training tones of the L-SIG field provide channel estimates for the data field. Power of the L-LTF field is managed relative to power of the L-SIG field in the generated symbol in a time domain.

Abstract: An interactive poster includes one or more first near-field communications (NFC) antennas, a memory to store first content, and a controller control operation of a display. The NFC antennas may be located at predetermined positions, and the controller changes display of first content to second content when one or more of the antennas are tapped by a user device including an NFC circuit.

Abstract: A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

Abstract: A calibration system of a digital phase locked loop (DPLL) includes a calibration circuit and a digitally controlled oscillator (DCO). The calibration circuit is configured to receive an input signal and a feedback signal, and generate a digital signal, based on a frequency of the input signal, a frequency of the feedback signal, and an input bias code. The DCO is configured to receive the input bias code and the digital signal, and generate a bias signal based on the input bias code. The DCO is further configured to generate an analog signal based on the bias signal and the digital signal, and generate the feedback signal such that the frequency of the feedback signal is based on an amplitude of the analog signal.

Abstract: A voltage differential sense amplifier circuit for a semiconductor memory circuit is disclosed. The voltage differential sense amplifier circuit includes a first and second pluralities of transistors. A first bias control circuit is included to bias the first plurality of transistors. The first bias control circuit is connected to body terminals of the first plurality of transistors for providing a temperature dependent first bias voltage to control threshold voltages of the first plurality of transistors. The temperature defendant first bias voltage is generated based on junction leakages at the body terminals of the first plurality of transistors. A second bias control circuit is included to bias the second plurality of transistors. The second bias control circuit is connected to body terminals of the second plurality of transistors for providing a temperature dependent second bias voltage to control threshold voltages of the second plurality of transistors.

Abstract: A DC-removing cascaded integrator-comb (CIC) filter circuit (40) includes N series-coupled integrator stages (401-405), a rate changer (406), and N series-coupled comb stages (407-411) which are configured to receive a CIC filter digital input signal and to generate a CIC filter digital output signal, wherein the N integrator stages include a first integrator stage (401) which includes a summation element (41) having first input for receiving a first input signal, a second input for receiving a second input signal, and an output coupled through a feedback delay element (42) to a multiplier element (43) which multiplies a DC-removing filter coefficient with an output of the feedback delay element to generate a product output that is provided to the second input of the summation element (41), thereby embedding a DC-removing filter in the N series-coupled integrator stages.

Abstract: A differential output driver circuit includes a drive path having a first output node that provides a first output differential signal and a second output node that provides a complementary second output differential signal to the first output differential signal, a current control transistor to control current of the drive path, and a current measurement resistor circuit located in the drive current path outside of a path segment between the first and second output node. Current flowing through the drive path flows through the current measurement resistor circuit, and a voltage across the current measurement resistor circuit is indicative of an amount of current flowing through the drive path. A transistor control circuit utilizes a voltage across the current measurement resistor circuit to control a control terminal of the current control transistor to control the current in the drive path based on the voltage across the current measurement resistor circuit.

Abstract: A method includes forming separate conductive trench structures in a trench and then removing an upper portion of one of the conductive structures where the remaining portion serves as field gate for a transistor. Removing the upper portion includes forming a second trench. The second trench is filled with a gate material that is used as a gate for the transistor. The transistor includes a source region for the transistor on the side of the trench and a drain region for the transistors on the other side of the trench, wherein the drain region includes a portion located at an upper portion of a semiconductor material. The transistor includes a channel region having a portion located along a sidewall of a trench.

Abstract: A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (VSUP1, VSUP2) to an output voltage node (VOUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (VSUP1, VSUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.

Abstract: Error detection circuitry is configured to receive raw read data from a memory, perform error detection in accordance with a single-bit error correction and double-bit error detection (SECDEC) error-correction code (ECC) on the raw read data, and provide a single bit correction indicator in response to performing the SECDEC ECC on the raw read data. Error correction circuitry is configured to provide corrected read data corresponding to the raw read data based at least on the single bit correction indicator. ECC checking circuitry is configured to generate a wrong operation indicator based at least on a parity of the raw read data, a parity of the corrected read data, and the single bit correction indicator, wherein the ECC checking circuitry is configured to assert the wrong operation indicator when at least one of the error detection circuitry or the error correction circuitry is not operating correctly.

Abstract: In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: digital logic for processing one or more portions of a data frame; a status detection unit configured to detect a status of a data frame reception or data frame transmission; a clock gating unit configured to apply clock gating to said digital logic in dependence on the status of said data frame reception or data frame transmission. In accordance with further aspects of the present disclosure, a corresponding method of operating a transponder is conceived, and a corresponding computer program is provided.

Abstract: A method, system, apparatus, and architecture are provided for detecting failure of a PCIe endpoint device by scanning an extended configuration space for each connected PCIe endpoint device to detect a first PCIe endpoint device that supports advance status reporting, and then by programming a first predetermined value and a second predetermined value, respectively, into an endpoint response register and a root complex request register of a dedicated memory control word in the extended configuration space for the first PCIe endpoint device, where the second predetermined value signals a request to the first PCIe endpoint device to update the endpoint response register of the dedicated memory control word with a new status value so that, after a minimum specified delay, a report that the first PCIe endpoint device has failed may be generated in response to detecting that the first predetermined value is stored in the endpoint response register.

Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.

Abstract: A galvanic isolation circuit comprising: a galvanic isolator having a first side and a second side; a first communication link connected to the first side of the galvanic isolator and connectable to a first transceiver a second communication link connected to the second side of the galvanic isolator and connectable to a second transceiver; a first reference terminal connectable to the first transceiver; a second reference terminal connectable to the second transceiver; and an AC short capacitor connected between the first reference terminal and the second reference terminal.

Abstract: The present application relates to a circuit and a transceiver comprising the circuit. The circuit comprises two bus line terminals for coupling to a bus and a bridge circuit comprising two legs. Each leg comprises an adjustable pull resistance and an adjustable push resistance connected in series with a respective one of the two bus line terminals. The adjustable pull resistances and the adjustable push resistances of the bridge circuit enable to independently adjust a driver impedance and to independently adjust a differential driver voltage on the bus. The circuit may further comprise an edge detector is coupled to a transmit data input and configured to detect a transition on the transmit data input and to adjust the impedances of the adjustable pull resistances and the adjustable push resistances in response to the detected transition.

Abstract: A circuit with a first transistor includes a first current electrode coupled to a first voltage supply, a second current electrode coupled to a first circuit node, and a gate electrode coupled to receive a first input signal. A second transistor includes a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a gate electrode coupled to receive a first bias voltage. A third transistor includes a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to a second circuit node, and a gate electrode. A fourth transistor includes a first current electrode coupled to the second circuit node, a second current electrode coupled to a third circuit node, and a gate electrode coupled to receive a second bias voltage. The gate electrode of the third transistor is coupled to the third circuit node.

Abstract: An intelligent transportation system, ITS, station (600) comprising: a host processor (640); and a memory (664) operably coupled to the host processor (640). The host processor (640) is configured to: perform verification per identity that includes precomputation of data for a plurality of neighbouring ITS stations of the ITS station (600); store precomputation data for the verified identity of the plurality of neighbouring ITS stations in the memory (664); and extract from memory (664) and use the stored precomputation data for a respective neighbouring ITS station to perform an accelerated verification of a subsequent message received from that neighbouring ITS station.

Abstract: A system and method for accessing a tagged global variable in software, including: randomly generating tags for global variables in the software; tagging the global variables with the random tags; creating a pointer to each global variable with the random tags in unused bits of the pointer wherein the pointer points to the associated global variable; accessing one global variable indirectly using the tagged pointer; determining whether tag on the accessed global variable matches the tag on the accessed pointer; and indicating a fault when the tag on the accessed global variable does not match the tag on the accessed pointer.

Abstract: An electrostatic discharge measuring device includes an integrated circuit including a collector, a discharge pad and an ESD detector circuit coupled to the collector and discharge pad. The ESD detector circuit includes a device that detects occurrence and magnitude of an electrostatic discharge between the collector and the discharge pad. In one embodiment, the device is a metal-oxide-semiconductor capacitor. In another embodiment, the device is a thin film storage bitcell. In one embodiment, the electrostatic discharge measuring device is contained in a test microelectronic package. A method includes running the test microelectronic package through a manufacturing process to determine location during manufacturing at which an electrostatic discharge occurs when an externally-similar production microelectronic packages is run through the same manufacturing process.

Abstract: System and method of configuring an external radar device through high speed reverse data transmission. In one embodiment, the system includes a radar data processing module for processing radar data received from the external radar device, and a radar configuration management module for generating control data for controlling the external radar device. The system further includes a configurable half-duplex interface, wherein the configurable half-duplex interface, in response to receiving a turnaround command, switches between (1) a configuration for transmitting control data packets to the external radar device via a communication link, and (2) a configuration for receiving radar data packets from the external radar device via the communication link.