Abstract: A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.

Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.

Abstract: A rectifier includes a first stage to convert an AC signal to a first rectified signal and a second stage to convert the AC signal to a second rectified signal. Each stage includes a MOSFET, a differential amplifier with a predetermined gain, and an analog buffer coupled to the output of the differential amplifier. The differential amplifier generates an amplified signal based on a difference between an input signal voltage and an output signal voltage. The analog buffer outputs a gate signal to switch the MOSFET based on the amplified signal. Switching of the MOSFET converts the AC signal corresponding to the input signal voltage to a corresponding one of the first rectified signal and the second rectified signal. The first and second rectified signals may be combined to form a DC signal for driving a load.

Abstract: A multi-voltage, high voltage I/O buffer in low-voltage technology is disclosed. In one embodiment, the I/O buffer includes a logic circuit configured to generate a signal based on a data signal and a first control signal. A level shifter is coupled between a supply voltage terminal and a ground terminal, and the level shifter is generates first and second output signals in first and second voltage domains, respectively, at first and second nodes, respectively, based on the signal from the logic circuit. A control circuit is coupled between the second node and a third node. The control circuit transmits the second output signal to the third node when the first control signal is asserted, and the control circuit couples the third node to the ground terminal when the first control signal is not asserted.

Abstract: A first communication device receives an aggregated data unit from a second communication device. The aggregated data unit aggregates (i) one or more sets of multiple data units, each set of multiple data units to be acknowledged by a respective block acknowledgement and (ii) one or more single data units, each single data unit to be acknowledged by a respective single acknowledgement. The first communication device generates a block acknowledgment frame that includes (i) block acknowledgement information to acknowledge the one or more sets of multiple data units, and (ii) single acknowledgment information to acknowledge the one or more single data units, where the block acknowledgement frame omits an indication that the block acknowledgement frame includes the single acknowledgement information. The first communication device causes the block acknowledgement frame to be transmitted to the second communication device.

Abstract: An integrated circuit (IC) is disclosed that includes a load circuit, and a voltage regulator circuit configured to provide a load voltage and a load current to the load circuit. The voltage regulator circuit can regulate the load voltage based on the load current.

Abstract: Embodiments of a method and device are disclosed. In an embodiment a controller is disclosed. In an embodiment, the controller includes a pulse width modulation (PWM) module configured to generate a sequence of pulses each having a width that is modulated by a PWM value stored in a register of the PWM module, a memory having a table of PWM values configured to be written into the PWM module register, a direct memory access (DMA) module coupled to the PWM module and to the memory table and configured to write a PWM value from the memory table into the PWM register in response to a DMA trigger, and a core coupled to the DMA module and configured to write the PWM values into the memory table.

Abstract: A method and device for detecting a malicious circuit on an integrated circuit (IC) device is provided. The method includes generating a plurality of test patterns on the IC. A scan test circuit and the plurality of test patterns are used to test don't care bits of a function under test on the integrated circuit. Scan out data from the scan test circuit is provided in response to the plurality of test patterns. The scan out data is stored in a memory on the integrated circuit. The scan out data is monitored over a predetermined time period. If it is determined that a characteristic of the scan out data has changed within the predetermined time period, an indication that a malicious circuit has been detected is output. The device includes circuitry for performing the method in the field.

Abstract: An integrated circuit includes a base current cancellation circuit and a complementary to absolute temperature (CTAT) circuit. The base current cancellation circuit includes a first bipolar junction transistor (BJT) and a current mirror coupled to the first BJT. The current mirror is configured to provide a mirrored current to a base electrode of the first BJT. The CTAT circuit is coupled to receive a voltage signal corresponding to a reference current of the current mirror. The CTAT circuit includes a second BJT coupled to form a base current based on the voltage signal.

Abstract: A first communication device generates a plurality of media access control (MAC) layer data units to be transmitted to a second communication device via a communication channel that includes a first frequency segment and a second frequency segment separated by a gap in frequency. The first communication device generates one or more physical layer (PHY) data units that include the plurality of MAC layer data units, and simultaneously transmits i) a first frequency portion of the one or more PHY data units via the first frequency segment, and ii) a second frequency portion of the one or more PHY data units via the second frequency segment, including transmitting a first MAC layer data unit in the first frequency portion, and ii) transmitting a second MAC layer data unit in the second frequency portion.

Abstract: According to a first aspect of the present disclosure an electronic device is provided, which comprises a non-conductive substrate and a touch-based user interface unit having a capacitive sensor structure, wherein said capacitive sensor structure comprises conductive wires embedded in the non-conductive substrate. According to a second aspect of the present disclosure a corresponding method of manufacturing an electronic device is conceived.

Abstract: A chip includes a first pin coupled to a signal line and a controller to detect a state of the signal line using the first pin. The controller controls output of first power to the signal line through the first pin based on a first state of the signal line and prevents output of the first power to the signal line through the first pin based on a second state of the signal line. The signal line may be coupled to provide second power from a power source to a data storage device.

Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which utilizes a filtered output of the analog-to-digital converter that has less distortion errors than the unfiltered output of the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.

Abstract: Embodiments are provided for a radar system including: an N number of transmit antennas; and an N number of phase shift keying (PSK) coders, each assigned a respective optimized transmitter code of a set of optimized transmitter codes, each optimized transmitter code of the set comprises a sequence of K code chips, each optimized transmitter code of the set is orthogonal to every other optimized transmitter code of the set, spectral analysis of a cross-correlation between any two optimized transmitter codes results in sidelobes no greater than a predetermined detection threshold, each PSK coder encodes K ranging waveform blocks according to the sequence of K code chips of the respective optimized transmitter code and produces a respective optimized coded sequence, and each of the N transmit antennas outputs the respective optimized coded sequence at the same time.

Abstract: A semiconductor device package having at least one integrated circuit (IC) die, at least two antennas oriented in at least two different directions, and a combiner/divider structure connecting the at least two antennas to the at least one IC die and configured to combine/divide signals transmitted between the at least two antennas and the at least one IC die. The package may be fabricated using an additive manufacturing process (i.e., 3D printing). In certain embodiments, the package is an integrated radio package having a multi-directional antenna array.

Abstract: A method is provided for protecting a trained machine learning model that provides prediction results with confidence levels. The confidence level is a measure of the likelihood that a prediction is correct. The method includes determining if a query input to the model is an attempted attack on the model. If the query is determined to be an attempted attack, a first prediction result having a highest confidence level is swapped with a second prediction result having a relatively lower confidence level so that the first and second prediction results and confidence levels are re-paired. Then, the second prediction result is output from the model with the highest confidence level. By swapping the confidence levels and outputting the prediction results with the swapped confidence levels, the machine learning model is more difficult for an attacker to extract.

Abstract: A current leg located in a voltage domain where the current leg includes a transistor of a current mirror having a maximum voltage rating of less than the voltage of the voltage domain. The current leg includes a resistive element circuit to provide a first resistance during a normal mode of operation of the current leg and a different resistance during of a stress test of the transistor in a test mode of the circuit.

Abstract: An electrostatic-discharge (ESD) protection circuit is provided. The circuit includes an I/O terminal coupled for receiving a signal having a negative voltage relative to a voltage supply terminal. An ESD transistor is formed in an isolated well. The transistor includes a control electrode and a first current electrode coupled to the I/O terminal. The isolated well is configured as a body electrode of the transistor. An ESD diode includes an anode electrode coupled to the voltage supply terminal and a cathode electrode coupled to a second current electrode of the transistor.

Abstract: Disclosed are methods and devices for deriving keys for coding the contents of data frames, which are to be transmitted in a keyless entry system during an ultra-wide band ranging session between a transceiver device coupled to a base structure to be opened and closed and/or to be locked and unlocked, and a mobile transceiver device associated with the structure-coupled transceiver device.

Abstract: Disclosed as a clock alignment module for a near field communication, NFC, controller operable in active load modulation, ALM, card mode, the module being operable during a transmit mode comprising transmit bursts and comprising: an input for receiving a field clock signal (CLK_FIELD); an output for outputting a local controller clock signal (CLK_FB); a transmit envelop unit configured to determine whether a time since an end of a latest transmit burst exceeds a threshold, Tdelay; and a phase locked loop, PLL, configured to selectively lock the phase of the local controller clock signal to the phase of the field clock signal, in response to the time exceeding the threshold and a next transmit burst not having started. Associated NFC controllers, integrated circuits and methods are also disclosed.