Abstract: An intelligent transportation system, ITS, station (600) comprising: a host processor (640); and a memory (664) operably coupled to the host processor (640). The host processor (640) is configured to: perform precomputation of certificate data associated with an identity to be verified on a per identity basis; store precomputation data for a plurality of verified identities in the memory (664); and extract stored precomputation data from memory (664) and use the stored precomputation data to perform accelerated verification of subordinate certificates.

Abstract: An open wire detection system and method are provided. A semiconductor device includes a first diode having an anode terminal coupled to a first terminal and a cathode terminal coupled to a second terminal. The first and second terminals are configured for connection to a first battery cell terminal by way of a first conductive path and a second conductive path. A detect circuit is coupled to the first diode and is configured to provide a first open wire indication when a first voltage across the first diode exceeds a first threshold.

Abstract: Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Abstract: There is disclosed a toy comprising a central unit and at least one peripheral unit which is operatively coupled to said central unit, wherein the central unit is arranged to establish Near Field Communication (NFC) with the peripheral unit, and wherein the central unit is further arranged to control one or more functions of the peripheral unit in dependence on control data received, via NFC, from said peripheral unit. Furthermore, a corresponding method for controlling a toy and a corresponding computer program product are disclosed.

Abstract: An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, an RF amplifier includes first and second RF signal paths having RF input interfaces, RF output interfaces, and corresponding transistors connected between the respective RF input interfaces and RF output interfaces, wherein control terminals of the transistors are connected to the RF input interfaces and current conducting terminals of the transistors are connected to the corresponding RF output interfaces. The RF amplifier including a conductive path between the current conducting terminal of the first transistor and the current conducting terminal of the second transistor, wherein the conductive path includes a first inductance, a second inductance, and a capacitance electrically connected between the first inductance and the second inductance.

Abstract: A shielded semiconductor device has a first die attached to a die pad of a lead frame and a second die attached to a surface of the first die. The first die is electrically connected to inner lead ends of leads that surround the die pad, and the second die is electrically connected to the first die and to an inner end of a shielding lead. A mold compound forms a body around the first and second dies and the electrical connections. Outer lead ends of the leads project from the sides of the body. The outer end of the shielding lead projects from a central location of one side of the body and is bent up the side surface from which it projects and over the top of the body and provides EMI shielding.

Abstract: A packaged radio frequency (RF) amplifier device includes a flange and a transistor die mounted to the flange. The transistor die includes an output terminal. The packaged RF amplifier device includes a first bond wire array including a first plurality of bond wires. Each bond wire in the first plurality of bond wires is electrically coupled to the output terminal of the transistor die. A first ground loop area of a first bond wire in the first plurality of bond wires is greater than a second ground loop area of a second bond wire in the first plurality of bond wires.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and further includes a first amplifier die, a second amplifier die, and a third amplifier die on the mounting surface. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path, the second amplifier die is configured to amplify a second RF signal along a second signal path, and the third amplifier die is configured to amplify a third RF signal along a third signal path. A side of the first amplifier die including a first output terminal faces a side of the second amplifier die including a second output terminal. The second signal path is parallel to the first signal path, and the third signal path is orthogonal to the first and second signal paths.

Abstract: An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.

Abstract: A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.

Abstract: Gate-protection circuitry protects a transistor, such as a MOSFET, from large gate-to-source voltage differentials that can permanently damage the transistor's gate-oxide layer. A source-voltage detector selectively enables the gate-protection circuitry based on a source voltage of the transistor. The gate-protection circuit is implemented without any Zener diodes. The transistor may be a load switch that is selectively controlled to apply a supply voltage to a load.

Abstract: A physical access point manages a first wireless communication sub-network and one or more second wireless communication sub-networks. The physical access point transmits values of wireless network management parameters for the first wireless communication sub-network to inform one or more client stations of the values of the wireless network management parameters for the first wireless communication sub-network. The access point generates a list of wireless network management parameters for which values are not inherited from the first wireless communication sub-network by any of the one or more second wireless communication sub-networks, and transmits the list to inform the one or more client stations that values of the wireless network management in the list are not inherited from the first wireless communication sub-network by any of the one or more second wireless communication sub-networks.

Abstract: A magnetoresistive random access memory (MRAM) array has a corresponding MRAM cell, including a Magnetic Tunnel Junction (MTJ), at an intersection of each row and column. A first row of the array is configured as a single one-time-programmable (OTP) row, wherein a first MRAM cell in a first column is connected to a second MRAM cell in a second column. A first MTJ of the first MRAM cell is connected to a first bit line of the first column, and a second MTJ of the second MRAM cell is not connected to a second bit line of the second column. During a write to the first MRAM cell, write circuitry is configured to connect the first and second bit lines and the corresponding source lines such that the select transistors in the first and second MRAM cells are connected in parallel to drive a write current through the first MTJ.

Abstract: A communication device includes a directional antenna, and a control circuit. The directional antenna has a directional radiation pattern for directing greater power of a transmitted signal in a specific direction. The control circuit is coupled to the directional antenna and determines an angle and a distance to another device. Based on the determined distance and angle to the another device, the control circuit selects a security level from a plurality of security levels for communication between the device and the another device. In another embodiment, a method for transmitting data between the first and second devices is provided.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating an ultra-wideband (UWB) device is disclosed. The method involves powering down a first receive path of a multipath UWB device while leaving a second receive path of the multipath UWB device powered up, powering down channel estimation, tracking, and demodulation functions of the second receive path, and performing an acquisition function using the second receive path while the first receive path is powered down and while the channel estimation, tracking, and demodulation functions of the second receive path are powered down.

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

Abstract: A mechanism is provided by which a hardware accelerator detects migration of a software process among processors and uses this information to write operation results to an appropriate cache memory for faster access by the current processor. This mechanism is provided, in part, by incorporation within the hardware accelerator of a mapping table having entries including a cache memory identifier associated with a processor identifier. The hardware accelerator further includes circuitry configured to receive a processor identifier from a calling processor, and to perform a look-up in the mapping table to determine the cache memory identifier associated with the processor identifier. The hardware accelerator uses the associated cache memory identifier to write results of called operations to the cache memory associated with the calling processor, thereby accelerating subsequent operations by the calling processor that rely upon the hardware accelerator results.

Abstract: A bias circuit is provided. The bias circuit includes a comparator circuit configured to compare a first voltage at a first input with a second voltage at a second input and generate a digital value at an output. A level shifter circuit is coupled to the comparator circuit. The level shifter is configured to receive a reference voltage at an input and generate the second voltage at an output. A charge pump circuit is coupled to the comparator circuit. The charge pump circuit is configured to generate the first voltage at an output based on the digital value.

Abstract: Embodiments of methods and systems for gain control in a communications device are described. In an embodiment, a method for gain control in a communications device involves detecting a change in an amplification gain that is applied to an analog signal in the communications device and compensating for the change in the amplification gain by manipulating an amplitude of a digital signal that is converted from the analog signal. Other embodiments are also described.