Abstract: An image sensor comprises a pixel array having a color filter array including a minimal repeating unit, where the minimal repeating unit consists of 4×4 pixels including two red pixels, four green pixels, two blue pixels, and eight clear pixels. When clear pixels are saturated and blooming, a blue pixel is affected by three or two clear pixels, but not four clear pixels.

Abstract: A chip-level camera includes an image sensor; a concave L1 lens element on an inside surface of a first substrate; a convex L2 lens element on a first surface of a second substrate; a diaphragm stop on a second surface of the second substrate or on a first surface of a third substrate, the diaphragm stop between the second and third substrates; a convex L3 lens element on a second surface of the third substrate spaced from the image sensor; a first spacer holding first substrate at a predetermined distance from the second substrate; and a second spacer holding the second substrate a predetermined distance from the image sensor. In embodiments, lens element L1 has concave aspheric radius of R1, and lens L2 convex aspheric radius of R2, such that 1.3<ABS(R2/R1)<2.2 and/or lens L3 has convex aspheric radius R3, where 1.1<ABS(R3/R1)<2.4.

Abstract: An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.

Abstract: A pixel circuit includes: a phototransistor configured to receive, by one region of a source and a drain, inflow of photo-carriers generated by light entering a substrate, and configured to output a voltage signal from the one region; and a blocking layer provided on another region of the drain and the source and on a side of a channel far from a surface, and configured to prevent the photo-carriers from directly flowing into the other region. The phototransistor causes a sub-threshold current to flow between the source and the drain in a pinch-off state. Each of the source and the drain of the phototransistor is periodically reset to a reset voltage. The reset voltage is set to a voltage between a voltage at which a dark current of the phototransistor becomes zero and a voltage at which a bias voltage of the phototransistor becomes zero.

Abstract: A pixel circuit includes: a photodiode configured to operate in a photovoltaic mode and to accumulate charges corresponding to an incident light amount; a reset transistor configured to reset the accumulated charges of the photodiode; and a peak hold circuit configured to hold an output corresponding to the accumulated charges of the photodiode, the peak hold circuit including a peak hold transistor connected to an output end of the photodiode, a switching transistor configured to turn on/off an output of the peak hold transistor, and a holding capacitor configured to hold an output of the switching transistor. The peak hold transistor operates in a state where no carrier charge or only one carrier charge is present on a channel.

Abstract: Transistors, electronic devices, and methods are provided. Transistors include a gate trench formed in a semiconductor substrate and extending to a gate trench depth, and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductive type. The source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, and the source and the drain each includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends to a depth in the semiconductor substrate deeper than the first doped region relative to a surface of the semiconductor substrate.

Abstract: An imaging system comprising a phase-detection image sensor comprising a plurality of phase-detection pixel units and a processor configured to: interpolate a green image to obtain a full resolution interpolated green image including defocused portions having artifacts and in-focus portions having sharp image, low-pass filter the full resolution interpolated green image to obtain a blurred image of the interpolated green image, combine the full resolution interpolated green image and the blurred image of the full resolution interpolated green image to obtain a corrected full resolution interpolated green image, where the artifacts of the defocused portions of the full resolution interpolated green image are removed, and the sharp image of the in-focus portions of the full resolution interpolated green image is unaffected.

Abstract: Electrical Phase Detection Auto Focus. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes configured to receive incoming light through an illuminated surface of the semiconductor material. The plurality of pixels includes at least one autofocusing phase detection (PDAF) pixel having: a first subpixel without a light shielding, and a second subpixel without the light shielding. Autofocusing of the image sensor is at least in part determined based on different electrical outputs of the first subpixel and the second sub pixels.

Abstract: A pixel of an image sensor includes a photodiode, a reset transistor, a peak hold transistor, and a first capacitor and a second capacitor. The pixels include, a first mode in which the noise and image output voltages of the photodiode are held in the first and second capacitors, respectively, and a second mode in which the output voltage of the photodiode in a state where the reset transistor is turned on to reset the photodiode is held in the first capacitor or the second capacitor. In the first mode, an image signal corresponding to the light incident amount of the photodiode and a noise signal when the light incident amount is relatively low are obtained. In the second mode, a noise signal when the light incident amount of the photodiode is relatively high is obtained.

Abstract: A pixel cell is formed on a semiconductor substrate having a front surface. The pixel cell includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate disposed on the front surface of the semiconductor substrate and a pair of vertical gate electrodes. Each vertical gate electrode extending a gate depth from the planar gate into the semiconductor substrate. The first junction depth is greater than the gate depth.

Abstract: An image sensor is an image sensor including a plurality of pixels. Each of the pixels includes a photodiode configured to generate charges based on a light incident amount, a reset transistor configured to reset the photodiode by supplying a reset voltage to the photodiode, a first capacitor configured to hold an output voltage of the photodiode immediately after the reset, and a second capacitor configured to hold the output voltage of the photodiode after a predetermined exposure period. An image signal is obtained from the voltage held by the first capacitor and the voltage held by the second capacitor.

Abstract: A cavity interposer has a cavity, first bondpads adapted to couple to a chip-type camera cube disposed within a base of the cavity at a first level, the first bondpads coupled through feedthroughs to second bondpads at a base of the interposer at a second level; and third bondpads adapted to couple to a light-emitting diode (LED), the third bondpads at a third level. The third bondpads coupled to fourth bondpads at the base of the interposer at the second level; and the second and fourth bondpads couple to conductors of a cable with the first, second, and third level different. An endoscope optical includes the cavity interposer an LED, and a chip-type camera cube electrically bonded to the first bondpads; the LED is bonded to the third bondpads; and a top of the chip-type camera cube and a top of the LED are at a same level.

Abstract: A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.

Abstract: A pixel circuit includes: a phototransistor configured to receive, by one region of a source and a drain, inflow of photo-carriers generated by light entering a substrate, and configured to output a voltage signal from the one region; and a blocking layer provided on another region of the drain and the source and on a side of a channel far from a surface, and configured to prevent the photo-carriers from directly flowing into the other region. The phototransistor causes a sub-threshold current to flow between the source and the drain in a pinch-off state. Each of the source and the drain of the phototransistor is periodically reset to a reset voltage. The reset voltage is set to a voltage between a voltage at which a dark current of the phototransistor becomes zero and a voltage at which a bias voltage of the phototransistor becomes zero.

Abstract: A pixel circuit including a transistor, a blocking layer and an output circuit is disclosed. The transistor includes a first doped region and a second doped region disposed on opposite sides of a channel of the transistor proximate to a first surface of a semiconductor substrate such that photo-carriers generated inside the semiconductor substrate in response to incident light flow into one region of the first and second doped regions. The blocking layer is disposed between the other region of the first and second doped regions and a second surface of the semiconductor substrate opposite to the first surface. The blocking layer configured to block the photo-carriers from flowing into the other region of the first doped region and the second doped region directly. The output circuit outputs an image signal according to a voltage signal outputted from the transistor.

Abstract: An image sensor comprises: a control block generating a video interface enabled signal, a video interface for receiving the video interface enabled signal, a pixel array for providing a video stream to the video interface, an output port for receiving the video stream from the video interface and outputting the video stream to outside of the image sensor, a stream indicator pin for receiving the video interface enabled signal from the control block when the video interface is receiving the video interface enabled signal from the control block, where a terminal of the video interface receiving the video interface enabled signal is connected to the stream indicator pin by a conductor, and they are sealed in a package of the image sensor.

Abstract: An image sensor comprises: a control block generating a video interface enabled signal, a video interface for receiving the video interface enabled signal, a pixel array for providing a video stream to the video interface, an output port for receiving the video stream from the video interface and outputting the video stream to outside of the image sensor, a stream indicator pin for receiving the video interface enabled signal from the control block when the video interface is receiving the video interface enabled signal from the control block, where a terminal of the video interface receiving the video interface enabled signal is connected to the stream indicator pin by a conductor, and they are sealed in a package of the image sensor.

Abstract: A method and apparatus for embedding a digital watermark in image content that is not visible to the human eye is performed on single-sensor digital camera images (often called ‘raw’ images) from a pixel-array. The raw image is transformed to generate preprocessed image coefficients, a watermark message is encrypted using a first key; the encrypted watermark message is randomized using a second key to form a watermark; and the watermark is embedded in randomly selected preprocessed image coefficients.

Abstract: An image sensor includes a semiconductor substrate and a multilayer film. The semiconductor substrate includes a photodiode and a back surface having a recessed region that surrounds the photodiode. The multilayer film is on, and conformal to, the recessed region, and includes N layer-groups of adjacent high-? material layers. Each pair of adjacent high-? material layers of a same layer-group of the N layer-groups includes (i) an outer-layer having an outer fixed-charge density and (ii) an inner-layer, located between the outer-layer and the recessed region, that has an inner fixed-charge density. Each of the outer and inner fixed-charge density is negative. The inner fixed-charge density is more negative than the outer fixed-charge density.

Abstract: A method for full interpolating green pixels from an input image having a first minimum repeating unit comprising 4×4 pixels, where 2×2 pixels of same color are grouped together, comprises down sampling of the input image to a first down sampled image, down sampling of the input image to a second down sampled image, and interpolating green pixels resulting in an interpolated green down sampled image, where the interpolating uses jointly the first down sampled image and the second down sampled image. The interpolated green pixels in an interpolated green down sampled image are further up sampled resulting in a full interpolated green image.