Patents Assigned to OmniVision Technologies, Inc.
  • Patent number: 11710752
    Abstract: A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal annulus. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region. The metal annulus (i) at least partially fills the trench, (ii) surrounds the small-photodiode region in the cross-sectional plane, and (iii) extends above the back surface. A method for fabricating a flicker-mitigating pixel-array substrate includes forming a metal layer (i) in a trench that surrounds the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region and (ii) on the back-surface region. The method also includes decreasing a thickness of an above-diode section of the metal layer located above the back-surface region.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 25, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yuanliang Liu, Bill Phan, Duli Mao, Hui Zang
  • Patent number: 11705475
    Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: July 18, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventor: Seong Yeol Mun
  • Patent number: 11706537
    Abstract: An image sensor includes a plurality of pixels that is arranged in a matrix and each of which outputs a signal in response to incident light, wherein readout of data can be performed with respect to the plurality of pixels, and simultaneous readout of data of a plurality of columns of pixels can be performed, and at least one pixel of the plurality of columns of pixels to be read simultaneously can be read for phase detection with respect to each of divided sub-pixels. The image sensor is configured to, with n rows as a readout unit where n is an integer of 2 or more, perform readout for at least one sub-pixel of at least one pixel in one readout cycle within the readout unit, perform readout for each pixel including phase detection readout for the other sub-pixel of the at least one pixel in which the at least one sub-pixel has been read in the one readout cycle, in another readout cycle within the readout unit, and end the readout for the readout unit with the n+1 readout cycles.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: July 18, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hiroki Ui, Eiichi Funatsu
  • Patent number: 11706543
    Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: July 18, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chengcheng Xu, Rui Wang, Bi Yuan, Liang Zuo
  • Publication number: 20230223413
    Abstract: Transistors include trenches formed in the semiconductor substrate having a first conductive type. The trenches define, in a channel width plane of the transistor, at least one nonplanar substrate structure having a plurality of sidewall portions and a tip portion disposed between the plurality of sidewall portions. An epitaxial overlayer is epitaxially grown on the sidewall portions and the tip portion. A channel doping layer having a doped portion of the semiconductor substrate is formed in the nonplanar substrate structure and enclosed by the epitaxial overlayer. An isolation layer is disposed in the trenches and over the epitaxial overlayer. A gate is disposed on the isolation layer and extends into the trenches.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 13, 2023
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Hui Zang, Gang Chen
  • Patent number: 11700464
    Abstract: A pixel cell includes a nitrogen-implanted region at a semiconductor material-gate oxide proximate interface located in a region above a photodiode. The pixel cell is further devoid of implanted nitrogen in channel regions of a plurality of pixel transistors. Thus, Si—N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, while the channel regions are protected from nitrogen implantation at the semiconductor material-gate oxide interface. Methods of forming the pixel cell are also described.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 11, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventor: Seong Yeol Mun
  • Publication number: 20230215887
    Abstract: The invention disclose a pixel in an image sensor capable of detecting infrared light and associated fabrication method. The image sensor includes a semiconductor substrate has a first photodiode and a second photodiode adjacent to the first photodiode. A planarized dielectric layer having a recessed region is disposed on a first side of the semiconductor substrate. A first color filter disposed on the planarized dielectric layer aligned with the first photodiode and configured to transmit light of a first wavelength range. A second color filter disposed in the recessed region and on the planarized dielectric layer. The second color filter is aligned with the second photodiode, and configured to transmit light of a second wavelength range that is different from the first wavelength range. A first depth-wise thickness of the first color filter is less than a second depth-wise thickness of the second color filter.
    Type: Application
    Filed: October 27, 2022
    Publication date: July 6, 2023
    Applicant: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Chen-Wei Lu, Jin Li, Shao-Fan Kao, Tung-Ti Yeh
  • Publication number: 20230215900
    Abstract: Pixels, such as for image sensors and electronic devices, include a photodiode formed in a semiconductor substrate, a floating diffusion, and a transfer structure selectively coupling the photodiode to the floating diffusion. The transfer structure includes a transfer gate formed on the semiconductor substrate, and a vertical channel structure including spaced apart first doped regions formed in the semiconductor substrate between the transfer gate and the photodiode. Each spaced apart first doped region is doped at a first dopant concentration with a first-type dopant. The spaced apart first doped regions are formed in a second doped region doped at a second dopant concentration with a second-type dopant of a different conductive type.
    Type: Application
    Filed: January 5, 2022
    Publication date: July 6, 2023
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Qin Wang, Hui Zang
  • Patent number: 11695944
    Abstract: A video encoding method includes (i) determining a current bit rate of a communication channel between a destination device and a source device that stores an input video frame, and (ii) generating a current reconstructed frame and an encoded bitstream at least in part via inter-frame coding of a current input video frame of a sequence of input video frames using a previously-generated reconstructed frame generated at least in part via inter-frame coding of a previous input video frame. The current reconstructed frame is a compressed version of the current input video frame. When both (i) a subsequent bit rate, determined after said inter-frame coding, is less than a threshold and (ii) the current bit rate exceeds the threshold, the method includes: (a) generating a downscaled reconstructed frame at least in part by downscaling the current reconstructed frame; and (b) appending the encoded bitstream with a bit sequence representing the downscaled reconstructed frame.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: July 4, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventor: Hitoshi Watanabe
  • Patent number: 11695030
    Abstract: A pixel-array substrate includes a semiconductor substrate, a buffer layer, and a metal annulus. The semiconductor substrate includes a first-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first-photodiode region. The buffer layer is on the back surface and has (i) a thin buffer-layer region located above the first-photodiode region and (ii) a thick buffer-layer region forming an annulus above the trench in a plane parallel to the cross-sectional plane. The metal annulus is on the buffer layer and covers the thick buffer-layer region.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 4, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventor: Seong Yeol Mun
  • Patent number: 11695029
    Abstract: A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 4, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen
  • Publication number: 20230207584
    Abstract: An image sensor element includes a transfer transistor TX, a LOFIC select transistor LF, a photodiode PD, and a first overflow path OFP. The transfer transistor TX outputs a readout signal from a first end. The LOFIC select transistor LF includes a first end connected to a second end of the transfer transistor TX, and a second end connected to a capacitor. The photodiode PD is connected in common to a third end of the transfer transistor and a third end of the LOFIC select transistor LF. The first overflow path OFP is formed between the photodiode PD and a second end of the LOFIC select transistor LF. Each of the transfer transistor TX and the LOFIC select transistor LF is configured with a vertical gate transistor.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: OmniVision Technologies, Inc.
    Inventor: Yoshiharu Kudo
  • Publication number: 20230207587
    Abstract: An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.
    Type: Application
    Filed: March 2, 2023
    Publication date: June 29, 2023
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Chiao-Ti Huang, Sing-Chung Hu, Yuanwei Zheng, Bill Phan
  • Publication number: 20230199341
    Abstract: An image sensor includes a plurality of pixels that is arranged in a matrix and each of which outputs a signal in response to incident light, wherein readout of data can be performed with respect to the plurality of pixels, and simultaneous readout of data of a plurality of columns of pixels can be performed, and at least one pixel of the plurality of columns of pixels to be read simultaneously can be read for phase detection with respect to each of divided sub-pixels. The image sensor is configured to, with n rows as a readout unit where a is an integer of 2 or more, perform readout for at least one sub-pixel of at least one pixel in one readout cycle within the readout unit, perform readout for each pixel including phase detection readout for the other sub-pixel of the at least one pixel in which the at least one sub-pixel has been read in the one readout cycle, in another readout cycle within the readout unit, and end the readout for the readout unit with the n+1 readout cycles.
    Type: Application
    Filed: April 7, 2022
    Publication date: June 22, 2023
    Applicant: OmniVision Technologies, Inc.
    Inventors: Hiroki Ui, Eiichi Funatsu
  • Patent number: 11683607
    Abstract: An imaging device includes a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light. The plurality of photodiodes includes first and second photodiodes. A shared floating diffusion receives charge transferred from the first and second photodiodes. An analog to digital converter (ADC) performs a first ADC conversion to generate a reference readout in response to charge in the shared floating diffusion after a reset operation. The ADC is next performs a second ADC conversion to generate a first half of a phase detection autofocus (PDAF) readout in response to charge transferred from the first photodiode to the shared floating diffusion. The ADC then performs a third ADC conversion to generate a full image readout in response to charge transferred from the second photodiode combined with the charge transferred previously from the first photodiode in the shared floating diffusion.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: June 20, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chengcheng Xu, Rui Wang, Wei Deng, Chun-Sheng Yang, Xueqing Wang
  • Patent number: 11683604
    Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: June 20, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Liang Zuo, Rui Wang, Selcuk Sen, Xuelian Liu, Min Qu, Hiroaki Ebihara
  • Patent number: 11683611
    Abstract: A pixel readout circuit includes an analog to digital converter coupled to the bitline output of the pixel circuit. A switch is coupled between the bitline output of the pixel circuit and a reference voltage. The switch is pulsed on and off a first time to settle the bitline to the reference voltage prior to an autozero operation of the analog to digital converter. The switch is pulsed on and off a second time to settle the bitline to the reference voltage after the autozero operation and prior to a first analog to digital conversion. The switch is configured to be pulsed on and off a third time to settle the bitline to the reference voltage after the first analog to digital conversion operation and prior to a second analog to digital conversion operation.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: June 20, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Zheng Yang, Ling Fu
  • Patent number: 11683602
    Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: June 20, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Sangjoo Lee, Rui Wang, Xuelian Liu, Min Qu, Liang Zuo, Selcuk Sen, Hiroaki Ebihara, Lihang Fan
  • Patent number: 11683598
    Abstract: An imaging system including an image sensor coupled to a controller to image an external scene is described. The controller includes logic storing instructions that when executed causes the imaging system to perform operations including capturing images, including a first image and a second image, of an external scene, and generating reduced representations of the images including a first reduced representation associated with the first image and a second reduced representation associated with the second image. The operations further include comparing the first reduced representation with the second reduced representation to determine a difference between the first image and the second image and identifying an occurrence of an occlusion affecting the image sensor imaging the external scene when the difference is greater than a threshold value.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: June 20, 2023
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Bo Mu, Boyd Fowler
  • Patent number: 11677011
    Abstract: A method of fabricating transistors with a vertical gate in trenches includes lithographing to form wide trenches; forming dielectric in the trenches and filling the trenches with flowable material; and lithography to form narrow trenches within the wide trenches thereby exposing well or substrate before epitaxially growing semiconductor strips atop substrate exposed by the narrow trenches; removing the flowable material; growing gate oxide on the semiconductor strip; forming gate conductor over the gate oxide and into gaps between the epitaxially-grown semiconductor strips and the dielectric; masking and etching the gate conductor; and implanting source and drain regions. The transistors formed have semiconductor strips extending from a source region to a drain region, the semiconductor strips within trenches, the trench walls insulated with a dielectric, a gate oxide formed on both vertical walls of the semiconductor strip; and gate material between the dielectric and gate oxide.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 13, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yuanliang Liu, Hui Zang