Abstract: A pixel-array substrate includes a semiconductor substrate, a buffer layer, and a metal annulus. The semiconductor substrate includes a first-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first-photodiode region. The buffer layer is on the back surface and has (i) a thin buffer-layer region located above the first-photodiode region and (ii) a thick buffer-layer region forming an annulus above the trench in a plane parallel to the cross-sectional plane. The metal annulus is on the buffer layer and covers the thick buffer-layer region.

Abstract: A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.

Abstract: An image sensor element includes a transfer transistor TX, a LOFIC select transistor LF, a photodiode PD, and a first overflow path OFP. The transfer transistor TX outputs a readout signal from a first end. The LOFIC select transistor LF includes a first end connected to a second end of the transfer transistor TX, and a second end connected to a capacitor. The photodiode PD is connected in common to a third end of the transfer transistor and a third end of the LOFIC select transistor LF. The first overflow path OFP is formed between the photodiode PD and a second end of the LOFIC select transistor LF. Each of the transfer transistor TX and the LOFIC select transistor LF is configured with a vertical gate transistor.

Abstract: An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.

Abstract: An image sensor includes a plurality of pixels that is arranged in a matrix and each of which outputs a signal in response to incident light, wherein readout of data can be performed with respect to the plurality of pixels, and simultaneous readout of data of a plurality of columns of pixels can be performed, and at least one pixel of the plurality of columns of pixels to be read simultaneously can be read for phase detection with respect to each of divided sub-pixels. The image sensor is configured to, with n rows as a readout unit where a is an integer of 2 or more, perform readout for at least one sub-pixel of at least one pixel in one readout cycle within the readout unit, perform readout for each pixel including phase detection readout for the other sub-pixel of the at least one pixel in which the at least one sub-pixel has been read in the one readout cycle, in another readout cycle within the readout unit, and end the readout for the readout unit with the n+1 readout cycles.

Abstract: A pixel readout circuit includes an analog to digital converter coupled to the bitline output of the pixel circuit. A switch is coupled between the bitline output of the pixel circuit and a reference voltage. The switch is pulsed on and off a first time to settle the bitline to the reference voltage prior to an autozero operation of the analog to digital converter. The switch is pulsed on and off a second time to settle the bitline to the reference voltage after the autozero operation and prior to a first analog to digital conversion. The switch is configured to be pulsed on and off a third time to settle the bitline to the reference voltage after the first analog to digital conversion operation and prior to a second analog to digital conversion operation.

Abstract: An imaging system including an image sensor coupled to a controller to image an external scene is described. The controller includes logic storing instructions that when executed causes the imaging system to perform operations including capturing images, including a first image and a second image, of an external scene, and generating reduced representations of the images including a first reduced representation associated with the first image and a second reduced representation associated with the second image. The operations further include comparing the first reduced representation with the second reduced representation to determine a difference between the first image and the second image and identifying an occurrence of an occlusion affecting the image sensor imaging the external scene when the difference is greater than a threshold value.

Abstract: An imaging device includes a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light. The plurality of photodiodes includes first and second photodiodes. A shared floating diffusion receives charge transferred from the first and second photodiodes. An analog to digital converter (ADC) performs a first ADC conversion to generate a reference readout in response to charge in the shared floating diffusion after a reset operation. The ADC is next performs a second ADC conversion to generate a first half of a phase detection autofocus (PDAF) readout in response to charge transferred from the first photodiode to the shared floating diffusion. The ADC then performs a third ADC conversion to generate a full image readout in response to charge transferred from the second photodiode combined with the charge transferred previously from the first photodiode in the shared floating diffusion.

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.

Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.

Abstract: An image sensor processor implemented method for retaining pixel intensity, comprising: receiving, by the image processor, a numerical value indicative of a corresponding pixel intensity; determining, by the image processor, whether a least significant portion of the received numerical value is equal to a predetermined numerical value; and responsive to determining the least significant portion of the received numerical value is equal to the predetermined numerical value, rounding, by the image processor, the received numerical value of the corresponding pixel intensity to a higher or lower value depending on a bit sequence, and if the least significant portion of the received numerical value is not equal to the predetermined value, rounding the received numerical value to the higher or lower value based on the received numerical value; and binning the rounded value.

Abstract: A method for detecting spoof fingerprints detected using an optical fingerprint sensor and polarization includes controlling a display of an electronic device to output a pattern of light to illuminate a fingerprint sample touching the display; blocking smaller-angle light from impinging a plurality of anti-spoof photodiodes of the pixel array; filtering larger-angle light incident on the plurality of anti-spoof photodiodes to at least one polarization direction; detecting the larger-angle light using the plurality of anti-spoof photodiodes; correlating the larger-angle light with the pattern of light; determining the fingerprint spoofing based at least in part on the correlation of the larger-angle light and the pattern of light; and wherein the plurality of anti-spoof photodiodes is interleaved with a plurality of imaging photodiodes such that each anti-spoof photodiode of the plurality of anti-spoof photodiodes is between adjacent imaging photodiodes of the plurality of imaging photodiodes.

Abstract: A method of fabricating transistors with a vertical gate in trenches includes lithographing to form wide trenches; forming dielectric in the trenches and filling the trenches with flowable material; and lithography to form narrow trenches within the wide trenches thereby exposing well or substrate before epitaxially growing semiconductor strips atop substrate exposed by the narrow trenches; removing the flowable material; growing gate oxide on the semiconductor strip; forming gate conductor over the gate oxide and into gaps between the epitaxially-grown semiconductor strips and the dielectric; masking and etching the gate conductor; and implanting source and drain regions. The transistors formed have semiconductor strips extending from a source region to a drain region, the semiconductor strips within trenches, the trench walls insulated with a dielectric, a gate oxide formed on both vertical walls of the semiconductor strip; and gate material between the dielectric and gate oxide.

Abstract: A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.

Abstract: A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal layer. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the small-photodiode region. The metal layer covers the first back-surface region, at least partially fills the trench, and surrounds the small-photodiode region in the cross-sectional plane. A method for fabricating a flicker-mitigating pixel-array substrate includes forming, on a back surface of a semiconductor substrate, a trench that surrounds a small-photodiode region of the semiconductor substrate in a cross-sectional plane parallel to a first back-surface region of the back surface above the small-photodiode region. The method also includes forming a metal layer on the first back-surface region and in the trench.

Abstract: An image sensor with passivated full deep-trench isolation includes a semiconductor substrate, the substrate including a plurality of sidewalls that form a plurality of trenches that separates pixels of a pixel array, and a passivation layer lining the plurality of sidewall surfaces and the back surface of the semiconductor substrate. A method for forming an image sensor with passivated full deep-trench isolation includes forming trenches in a semiconductor substrate, filling the trenches with a sacrificial material, forming a plurality of photodiode regions, forming a circuit layer, thinning the semiconductor substrate, and removing the sacrificial material. A method for reducing noise in an image sensor includes removing material from a semiconductor substrate to form a plurality of trenches that extend from a front surface toward a back surface, and depositing a dielectric material onto the back surface and into the plurality of trenches through a back opening of each trench.

Abstract: A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.

Abstract: A device includes a photodiode, a floating diffusion region, a transfer gate, and a channel region. The photodiode is disposed in a semiconductor material. The photodiode is coupled to generate charge in response to incident light. The floating diffusion region is disposed in the semiconductor material. The transfer gate is disposed between the photodiode and the floating diffusion region. The channel region associated with the transfer gate is in the semiconductor material proximate to the transfer gate. The transfer gate is coupled to transfer the charge from the photodiode to the floating diffusion region through the channel region in response to a transfer signal coupled to be received by the transfer gate. The transfer gate includes a plurality of fin structures that extend into the semiconductor material and the photodiode.

Abstract: A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

Abstract: A device includes a photodiode, a floating diffusion region, a transfer gate, and a channel region. The photodiode is disposed in a semiconductor material. The photodiode is coupled to generate charges in response to incident light. The photodiode has a substantially uniform doping profile throughout a depth of the photodiode in the semiconductor material. The floating diffusion region is disposed in the semiconductor material. The transfer gate is disposed between the photodiode and the floating diffusion region, wherein the transfer gate includes a plurality of fin structures. The channel region associated with the transfer gate is in the semiconductor material proximate to the transfer gate. The transfer gate is coupled to transfer the charge from the photodiode to the floating diffusion region through the channel region in response to a transfer signal coupled to be received by the transfer gate.