Abstract: A method of image sensor package fabrication includes forming a recess in a transparent substrate, depositing conductive traces in the recess, inserting an image sensor in the recess so that the image sensor is positioned in the recess to receive light through the transparent substrate, and inserting a circuit board in the recess so that the image sensor is positioned between the transparent substrate and the circuit board.

Abstract: A ramp generator includes a plurality of switched current sources coupled in parallel between a resistor and ground. A digital ramp control signal generator includes a counter to generate a ramp control signal in response to a clock signal. Each bit of the ramp control signal is coupled to control switching of a respective one of the plurality of switched current sources to generate a ramp signal at an output of the ramp generator. The digital ramp control signal generator is coupled to receive a reset signal to zero the ramp control signal. The digital ramp control signal generator is further coupled to receive a set bits signal to initialize the ramp signal to a preset value after every reset of the ramp control signal to add a DC offset compensation current determined by the preset value to the ramp signal.

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. At least three substrate trench structures are formed in the semiconductor substrate, defining two nonplanar structures, each having a plurality of sidewall portions. An isolation layer includes at least three isolation layer trench structures, each being disposed in a respective one of the three substrate trench structures. A gate includes three fingers, each being disposed in a respective one of the three isolation layer trench structures. An electron channel of the transistor extends along the plurality of sidewall portions of the two nonplanar structures in a channel width plane.

Abstract: Transistors include a pyramid-shaped gate trench defined by a triangular shape or a trapezoidal shape in a channel width plane and a trapezoidal shape in a channel length plane. Side wall portions of the pyramid-shaped gate trench form a channel having a triangular shape or a trapezoidal shape in the channel width plane. Advantageously, such transistors increase transconductance without increasing pixel width. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Abstract: A method for detecting spoof fingerprints with an under-display fingerprint sensor includes illuminating, with incident light emitted from a display, a target region of a fingerprint sample disposed on a top surface of the display; detecting a first scattered signal from the fingerprint sample with a first image sensor region of an image sensor located beneath the display, the first image sensor region not directly beneath the target region, the first scattered signal including a first portion of the incident light scattered by the target region; determining a scattered light distribution based at least in part on the first scattered signal; and identifying spoof fingerprints based at least in part on the scattered light distribution.

Abstract: An imaging system includes a pixel array configured to generate image charge voltage signals in response to incident light received from an external scene. An infrared illumination source is deactivated during the capture of a first image of the external scene and activated during the capture of a second image of the external scene. An array of sample and hold circuits is coupled to the pixel array. Each sample and hold circuit is coupled to a respective pixel of the pixel array and includes first and second capacitors to store first and second image charge voltage signals of the captured first and second images, respectively. A column voltage domain differential amplifier is coupled to the first and second capacitors to determine a difference between the first and second image charge voltage signals to identify an object in a foreground of the external scene.

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. The transistor includes a nonplanar structure disposed in the semiconductor substrate, which is bounded by two outer trench structures formed in the semiconductor substrate. Isolation deposits are disposed within the two outer trench structures formed in the semiconductor substrate. A gate includes a planar gate and two fingers extending into one of two inner trench structures formed in the semiconductor substrate between the nonplanar structure and a respective one of the two outer trench structures. This structure creates an electron channel extending along a plurality of sidewall portions of the nonplanar structure in a channel width plane.

Abstract: An image sensor module comprises an image sensor having a light sensing area, a cover glass for covering the light sensing area, a dam between the image sensor and the cover glass, which surrounds the light sensing area, and has an outer wall and an inner wall, where a cross-section of the inner wall parallel to the surface of the light sensing area of the image sensor forms a sawtooth pattern and/or, where a cross-section of the inner wall orthogonal to the surface of the light sensing area of the image sensor forms an inclined surface.

Abstract: Reference clock CMOS input buffer with self-calibration and improved ESD performance. In one embodiment, a reference clock input buffer of an image sensor includes a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge. The falling edge and the rising edge are separated by a hysteresis voltage. The Schmitt trigger includes a plurality of output switches and a plurality of voltage control switches that are individually coupled to individual output switches [M2-i] of the plurality of output switches. Voltage of the falling edge signal or the rising edge signal of the Schmitt trigger is adjustable by selectively switching at least one voltage control switch of the plurality of voltage control switches.

Abstract: An image sensor comprises a first photodiode, a second photodiode, and a deep trench isolation structure. The first photodiode and the second photodiode are each disposed within a semiconductor substrate. The first photodiode is adjacent to the second photodiode. The deep trench isolation structure has a varying depth disposed within the semiconductor substrate between the first photodiode and the second photodiode. The DTI structure extends the varying depth from a first side of the semiconductor substrate towards a second side of the semiconductor substrate. The first side of the semiconductor substrate is opposite of the second side of the semiconductor substrate.

Abstract: An optical fingerprint sensor with spoof detection includes a plurality of lenses; a pixel array including a plurality of first photodiodes, a line between a center of each first photodiode and an optical center of each lens forms an optical axis; at least one apertured baffle-layer positioned between the image sensor and the plurality of lenses, each having a respective plurality of aperture stops, each aperture stop being center-aligned with the optical axis; and a plurality of second photodiodes intercalated with the plurality of first photodiodes; and a color filter layer between the pixel array and the plurality of lenses, said color filter layer includes a plurality of color filters positioned such that each second photodiode is configured to detect electromagnetic energy having passed through lens, a color filter, and at least one aperture stop not aligned along the optical axis.

Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Abstract: A surface-mount device platform includes a surface-mounting region, a connection region, and a bendable region therebetween, each including a respective part of a base substrate. The base substrate includes electrically-conductive layers interspersed with electrically-insulating build-up layers. Each of the surface-mounting region, the connection region, and the bendable region spans between a bottom substrate-surface and a top substrate-surface of the base substrate. The surface-mounting region further includes an electrically-insulating first top rigid-layer, and device bond-pads exposed on a top surface of the first top rigid-layer facing away from the top substrate-surface in the surface-mounting region.

Abstract: A photodiode array has buried photodiodes and vertical selection transistors. Trenches are lined with gate oxide and metallic plugs of first material lie within the trenches. Gate contacts of second material contact the metallic plugs, with photodiode diffusion regions adjacent the trenches as sources of vertical transistors, the metallic plugs form gates of the vertical transistors, and buried photodiode regions form sources of the vertical transistors. In embodiments, the first conductive material is tungsten, titanium nitride, titanium carbide, or aluminum and the second conductive material is polysilicon. The array is formed by trenching, growing gate oxide, and depositing first material in the trenches. The first material is etched to define metallic plugs, the second material is deposited onto the metallic plugs then masked and etched; and drain regions implanted. Etching the second material is performed by a reactive ion etch that stops upon reaching the metallic plugs.

Abstract: A pixel-array substrate includes a semiconductor substrate and a passivation layer. The semiconductor substrate includes a pixel array surrounded by a periphery region. A back surface of the semiconductor substrate forms, in the periphery region, a plurality of first peripheral-trenches extending into the semiconductor substrate. The passivation layer is on the back surface and lines each of the plurality of first peripheral-trenches.

Abstract: An event sensing system includes a pixel array including a plurality of event driven pixel circuits configured to be illuminated by incident light. The event driven pixel circuits are configured to generate an event current in response to a detection of an event in the incident light. Output signals of a row of the pixel array are configured to be read out from the row of the pixel array to a line buffer in response to the detection of the event in the incident light. A random number generator is configured to randomly generate a filtering mask. A mask circuit is the output signals of the row of the pixel array from the line buffer and the filtering mask from the random number generator to filter the output signals of the row of the pixel array in response to the filtering mask.

Abstract: A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern formed using laser marking on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the at least one code pattern is visible from a backside of the chip, the at least one code pattern represents a binary number having four bits; and the binary number represents a decimal number to represent a tracing number of the chip.

Abstract: An image sensor with embedded wells for accommodating light emitters includes a semiconductor substrate including an array of doped sensing regions respectively corresponding to an array of photosensitive pixels of the image sensor. The semiconductor substrate forms an array of wells. Each well is aligned with a respective doped sensing region to facilitate detection, by the photosensitive pixel that includes said respective doped sensing region, of light emitted to the photosensitive pixel by a light emitter disposed in the well. The image sensor further includes, between adjacent doped sensing regions, a light-blocking barrier to reduce propagation of light to the doped sensing-region of each photosensitive pixel from wells not aligned therewith.

Abstract: A high k passivation layer, an anti-reflective coating layer, and a buffer layer are disposed over semiconductor substrate including photodiodes formed therein. Trenches are etched into the semiconductor substrate through the buffer layer, anti-reflective coating layer, and the high k passivation layer in a grid-like pattern surrounding each of the photodiodes in the semiconductor substrate. Another high k passivation layer lines an interior of the trenches in the semiconductor substrate. An adhesive and barrier layer is deposited over the high k passivation layer that lines the interior of the trenches. A deep trench isolation (DTI) structure is formed with conductive material deposited into the trenches over the adhesive and barrier layer to fill the trenches. A grid structure is formed over the DTI structure and above a plane of the buffer layer. The grid structure is formed with the conductive material.